1 Assessment of the potential value return from research topics Follow-up IRC actions from ITRS Maastricht, 04/07/06 July ITRS IRC Plenary inputs Incl. Three Scaling-Related Definitions Proposal, Rev /10/06

2 Food for thought from the IRC Moores Law and its continuance is an economic rather than a technical statement (Bernard Meyerson, chief technologist for IBMs Systems & Technology Group). Clock frequency is not the [only] driver of system performance. You can get a better result by making tradeoffs to balance numerous aspects of performance (adapted from Bernard Meyerson) Classical Scaling -- the glue that connects Moores Law to performance – is enhanced by equivalent scaling. There are additional ways to enhance economic and technical performance in conjunction with, or without, scaling.

3 Pursuing the race for added value for the end customer by combining on-chip ULSI and off-chip integration More than Moore: Diversification More Moore: Miniaturization Combining SoC and SiP: Higher Value Systems Baseline CMOS: CPU, Memory, Logic Biochips Sensors Actuators HV Power Analog/RFPassives 130nm 90nm 65nm 45nm 32nm 22nm. V Information Processing Digital content System-on-chip (SoC) Interacting with people and environment Non-digital content System-in-package (SiP) Beyond CMOS 2005 edition [Geometrical + Equivalent Scaling]

4 Three Scaling-Related Definitions Glossary Proposal In order to clarify the IRC/TWG work on innovation and value, below is a proposal for three scaling- related definitions to be added to the Executive Summary Glossary in the 2006 Update: 1)Geometrical (constant field) Scaling (More Moore) refers to the continued shrinking of horizontal and vertical physical feature sizes of the on-chip logic and memory storage functions in order to improve density (cost per function reduction) and performance (speed, power) and reliability values to the applications and end customers. Examples (not exhaustive) are: a) horizontal half-pitch feature size (f^2) for density/cost; b) gate insulator thickness for speed and power performance; c) gate length for speed performance. Slowing of geometrical scaling reduces the rate at which the end applications and customers receive value benefits, requiring new equivalent scaling material and/or gate enhancements. 1+) Equivalent Scaling which occurs in conjunction with, and also enables, continued Geometrical Scaling, refers to 3-dimensional device structure (Design Factor) Improvements plus other non-geometrical process techniques and new materials that affect the electrical performance of the chip. Examples (not exhaustive) are: a) horizontal or vertical function design factor (i.e. 3-dimensional capacitor and transistor designs); b) strained silicon in the transistor gate; c) flash memory electrical multi-bit-cell; d) high-K capacitor material for enhanced DRAM storage effectiveness; e) high-K transistor gate material substitutes for insulator thickness scaling; f) low-K chip-level interconnect material. Electrical equivalent scaling can enhance the value benefits of geometrical scaling.

5 Three Scaling-Related Definitions Glossary Proposal [Definitions continued] 2) More than Moore refers to System-on-Chip (SOC) and/or System-in-Package (SIP) techniques and materials that provide additional chip, board, and system-level cost and performance value to the application and end customer, in conjunction with geometrical and equivalent scaling. Examples (not exhaustive) are: a) Large cache memory management architecture; b) Multi-core MPU architecture; c) on-chip logic plus software power management; d) stacked chips with through-vias for board-level density and power; e) Packaging low-K interconnect materials; and f) diverse Specialized Functionality such as AMS/RF, Image Sensors, Sensors/Actuators (including MEMS), Embedded Passives, etc.

6 Three Scaling-Related Definitions Glossary Proposal and Examples Outline (including value to application/customer) 1.More Moore (MM) - Geometrical (constant field) scaling a)Horizontal – half-pitch feature size (f 2 ) (Moores Law, Function Size, Density) b)Vertical – Gate Insulator Thickness (limit of Silicon Oxide) (Performance – speed, power) c)Horizontal – Gate Length (Performance – speed, power) (1+). Equivalent scaling - Device Design and Process Techniques a) Vertical function design factor for density/cost, i.e. 3-D capacitor and transistor designs (Density/cost, Performance – speed, power) b) Strained Silicon (enhances gate current performance without gate insulator thickness reduction, while horizontal gate length continues to scale) MPU/ASIC (Performance – speed, power) c) Flash bit multi-cell (Density/cost) - Materials d)High K Capacitor DRAM (Performance – Storage Effectiveness/Reliability) e) High K Gate MPU/ASIC (enhances gate performance without vertical scaling, while horizontal gate length continues to scale) (Performance – speed, power) f)Low K Interconnect (Performance – speed, power) 2.More Than Moore (MtM) – Additional SOC and/or SIP, in conjunction with, or without, Geometrical and Equivalent chip scaling (chip, package, board, and system-level density/cost, performance - speed and power) a)Large Cache b)Multi-core c)On-chip logic plus software power management d)Stacked Chips with through-vias e)Package Low-K Interconnect Material f)Specialized Functionality AMS/RF Image Sensors Sensors/Actuators (including MEMS) Embedded Passives Etc.

7 Follow-up process Start working now on the subject of equivalent scaling parameters –Topic to be included in the TWG meetings Conference call early June –Joint conf call with IRC / some TWG chairs Summer meeting –Half-day workshop IRC / selected TWG chairs Contact with other consortia –MEMS Industry group (A.Allan) –iNEMI (A.Allan, JA.Carballo) –IEEE (P.Gargini)

8 To be discussed in the TWG meetings Former approach –Economic value through dimensional scaling Proposed Approach –It is appropriate to evaluate the benefit of the addition of beyond Moore with respect to the customer. –The IRC wants the TWGs to think out of the box and look beyond geometrical (constant field) and equivalent scaling

9 Possible topics that may interact with the economic value issue. Working groups will continue to give input throughout 2006 for 2007 ITRS What are other drivers? How do we bring additional value to the customer - multi-dimensional and may need to think how best to guide research. Questions for the CrossTWG meeting with the five teams [Interconnect, Design, PIDS, Wireless and A&P] TWG – 1.What value/benefit will pure continuing geometrical (constant field) and equivalent scaling bring ? 2.Which non-scaling (More than Moore) parameters will bring scaling-like value, such as: meeting system performance/cost, or bringing additional functionalities? 3.How to characterize / evaluate non-scaling parameters (of 2.) versus the continuing scaling approach? 4.Are there trade-offs involved between scaling and non-scaling parameters (e.g., frequency vs. # of multi-core processors)? 5.Is a cost-to-value tool needed to help evaluate trade-offs? What are the appropriate inputs/outputs for such a cost model? 6.The generic ITRS pre-competitive boundary timing is set by scaling and should be two technology generations (0.7x) from current technology level – What is the pre-competitive boundary for the potential solution topic? 7.What is the necessary critical mass of interested companies?

10 Possible TWG involvement preparation/proposals for July ITRS Assy & Packaging –System integration white paper –Passive integration Design –Extension of roadmap / system drivers (example Automotive HV power, Sensors) –System on Chip / network on Chip PIDS / Design –extending MASTAR to system level Interconnect –Optical –Passive integration RF Wireless –Passive integration …

11 Format proposal TWGFunctionalityTechnical Parameter 1 …Value Indicator = f(TP1, …TPn) AMS / RFMulti-standard adaptability # of standardsBroader application scope AMS / RFPassive integration Inductor QLower system cost Design PIDS Image sensorsQuantum efficiency Image quality Dont feel restricted by that format ! Thinking out of the box is welcome !

12 Citation P. Cogez More Moore and More than Moore Illustrations

13 Source: STM, ITRS IRC meeting – ca. July, 2006 Illustration: Geometrical Scaling (Constant Electric Field)

14 Citation, slide 13 Is there still plenty of room at the bottom? Claude Weisbuch, LMC Polytechnic, and Michel Brillouet, CEA/LETI, Grenoble

15 Litho cost trend 193 nm 13.5 nm ~ 50 $ M Source: STM, ITRS IRC meeting – ca. July, 2006 Illustration: Geometrical Scaling (Litho Cost Issues)

16 New DG SON – among best results ever reported Moores Laws can be prolonged beyond 22nm ! But ……..… -> Improvements of CMOS structure to cope with challenges Source: STM, ITRS IRC meeting – ca. July, 2006 Illustration: Geometrical Plus Equivalent Scaling

17 New Materials FEOL Starting Material BEOL 1960 Si SiO, SiN Al 1970 (B)PSG Si,Epi SiO, SiN Al-Si 1980 Si(O)N WSi, MoSi TiW (B)PSG Si,Epi SiO, SiN Al-Si-Cu 1990 TiSi Si(O)N WSi, PtSi Ti/TiN (B)PSG Si,Epi SiO, N Al-Cu W Year 2000 Cu SiOF SiGe CoSi Si(O)N W, WSi Ti/TiN (B)PS G Si,epi SiO, N Al-Cu SOP SiOC W TaO Ta/Ta N SOI Str. Si Porous SiOC Cu SiOF SiGe NiSi Si(O)N W, WSi Ti/TiN (B)PS G Si,epi SiO,,N AlCu SOP SiOC W AlO Hf(Si) O Ta/Ta N TaO Cu SiOF SiGe TiSi Si(O)N W,WSi Ti/TiN (B)PS G Si,Epi SiO, N Al-Cu W Ta/Ta N 1995 …and more coming in 2010… Note the Scale Change From E. Kamerbeek, ASM Source: STM, ITRS IRC meeting – ca. July, 2006 Illustration: Equivalent Scaling (Cumulative Material Cost Issues)

18 Smaller Chips, Higher Entry Costs 150 mm 100 mm 200 mm 300 mm Surface proportional to cost M$ 5µ-> 0.8µ 70 M$ 20µ-> 5µ Production At each step, production capacity doubles and critical dimensions halve 2-4 B$ 0.1µ -> 0.032µ 1-2 B$ 0.5µ -> 0.13µ R&D R&D costs by generation ~1 B$ 250nm 180nm 130nm 90nm Source: STM, ITRS IRC meeting – ca. July, 2006 Illustration: Equivalent Scaling (Cumulative R&D Cost Issues) Illustration: Scaling (Fab Cost Issues) Illustration: Scaling (Technology R&D Cost Issues)

19 iNEMI Vision of the Evolution of SiP (International Electronics Manufacturing Initiative) Source: Professor Rao Tummala, Georgia Institute of Technology-Packaging Research Center. Source: STM, ITRS IRC meeting – ca. July, 2006 Illustration: Scaling plus More than Moore

20 Differentiation challenges How to predict future applications? Projection done in 1954 of home computer in 2004 Source: STM, ITRS IRC meeting – ca. July, 2006

21 Maybe turn to cartoonists ? Illustration of Moores original article (1965)

22 Backup

23 Technology Evolution CMOS baselinememoryRF HV Powerpassives sensors actuators bio, fluidics Non-CMOS devices, multi-chip, SiP solutions Moores Law size [nm]

24 Past –Geometrical Scaling (G) Moores Law Future –Equivalent Scaling (E) More Moore + Functional Diversification More than Moore (MtM) (digital) (non-digital)

25 1/2 G P E + MtM + New P P 1/2

26.7 ~17%-50% ~.7~17%-3050% VHPC G E - Transistor - Interconnect - Capacitor