ITRS Design + System Drivers July, 2010 Design ITWG Juan-Antonio Carballo Tamotsu Hiwatashi William Joyner Andrew Kahng Noel Menezes Shireesh Verma Good morning. Here we present the work that the ITRS Design TWG has pursued in 2007, and describe the continuation of this work into our 2008 strategy.

Overview (2004-Today) 1. Increasingly quantitative roadmap 2 Overview (2004-Today) 1. Increasingly quantitative roadmap 2. Increasingly complete driver set 2010 2009 MTM RF+AMS Driver Updated Consumer, MPU, and Networking Drivers Power roadmap chart Upgraded RF+AMS section 2008 MTM extension + iNEMI synch + SW !! MTM extension + iNEMI + SW !! 2007 More Than Moore (MTM) analysis + iNEMI Updated Consumer Stationary, Portable architecture, and Networking Drivers 2006 Updated Consumer Stationary, Portable, and Networking Drivers 2005 Consumer Stationary, Portable, Networking Drivers Consumer Stationary, Portable Drivers ******* Do the same here as in the prior slide that looks the same – except here focus on the system drivers piece of it, and how it has evolved over the years ******* As this slides summarizes, we have been following a consistent successful strategy in the last years. There are two components to this strategy. First, we have been assembling a quantified Design Technology roadmap, one that resembles in structure the other non-Design chapters in our roadmap, a necessary improvement. Second, we have been assembling a comprehensive set of system drivers aligned by segment, thereby mirroring the increasing segmentation in the semiconductor industry. As you can see in the chart, we have been successful. Our Design Technology roadmap includes numerous metrics and carefully matching text sections in the Design Chapter. Our System Drivers chapter has been adding several new drivers over the last few years. This work, however, needs to continue and be updated yearly. Lastly, in 2007 we have started adding explicit content about More Than Moore and have started aligning our chip roadmap with the leading system roadmaps, specifically iNEMI. 2004 Consumer Portable Driver Additional Design Metrics DFM Extension System level extension System Drivers Chapter Driver study Revised Design Metrics DFM extension Revised Design Technology Metrics Revised Design metrics Explore Design metrics Design Technology metrics Design Chapter 2011 Roadmap Work in Progress – Do Not Publish! 2 2

Selected Messages 2010 Design productivity continues to be center focus of design technology roadmap, as scaling depends on time to market Accurate design productivity and cost models are key Power consumption has become the key technical parameter that controls feasible semiconductor scaling Power-driven device roadmap, frequency pushed to flat trend More Than Moore has become a necessary component of semiconductor product scaling Mixed SiP-SoC analog-digital drivers need to be roadmapped While we had already assembled a Design Technology Roadmap, in 2007 we did quite a few improvements and updates. We start with the “cosmetic” ones – specifically we have made a big effort to make the chapter more concise and consistent, with every section approximately the same size, including its text and its tables. 3

Design / System Drivers 2010*-2011* Plans Design chapter Improvement of design productivity and cost models * Develop “Power Chart” based on STRJ & productivity chart * Ensure 3D / TSV content consistent with other chapters * Improve DFM section, including Design for reliability rows * Overhaul of Verification *, L/C/P sections * System Drivers chapter Update MPU frequency roadmap (flat trend), evaluate impact * Update of SOC-CP and SOC-CS models (driven from TWGs) * Update AMS/RF Driver / fabric with Wireless TWG * More-Than-Moore RF+AMS driver SiP-SoC (based on SoC-P) * Other Cross-TWG and public activity PIDS: increase design-driven requirements definition * 3D/TSV: hold for ACTION * Continue other key interactions: A&P, Interconnect, Test * Incorporate input from 2nd EDA Roadmap Workshop (@DAC)* While we had already assembled a Design Technology Roadmap, in 2007 we did quite a few improvements and updates. We start with the “cosmetic” ones – specifically we have made a big effort to make the chapter more concise and consistent, with every section approximately the same size, including its text and its tables. 4

Design / System Drivers 2010*-2011* Plans Design chapter Improvement of design productivity and cost models * Develop “Power Chart” based on STRJ & productivity chart * Ensure 3D / TSV content consistent with other chapters * Improve DFM section, including Design for reliability rows * Overhaul of Verification *, L/C/P sections * System Drivers chapter Update MPU frequency roadmap (flat trend), evaluate impact * Update of SOC-CP and SOC-CS models (driven from TWGs) * Update AMS/RF Driver / fabric with Wireless TWG * More-Than-Moore RF+AMS driver SiP-SoC (based on SoC-P) * Other Cross-TWG and public activity PIDS: increase design-driven requirements definition * 3D/TSV: hold for ACTION * Continue other key interactions: A&P, Interconnect, Test * Incorporate input from 2nd EDA Roadmap Workshop (@DAC)* While we had already assembled a Design Technology Roadmap, in 2007 we did quite a few improvements and updates. We start with the “cosmetic” ones – specifically we have made a big effort to make the chapter more concise and consistent, with every section approximately the same size, including its text and its tables. 5

ITRS Design Productivity Roadmap Model for upcoming Power Management Roadmap RTL Functional Verif. Tool Suite IC Implementation Tool Set Transaction Level Modeling System Design Automation AMP Parallel Processing Many Core Devel. Tools SMP Parallel Processing Executable Specification Very large block reuse Transactional Memory Intelligent Testbench Source: ITRS

Design Productivity INNOVATIONS Design Cost ITRS Design Productivity Roadmap Model for upcoming Power Management Roadmap Design Productivity INNOVATIONS RTL Functional Verif. Tool Suite IC Implementation Tool Set Transaction Level Modeling System Design Automation AMP Parallel Processing Many Core Devel. Tools SMP Parallel Processing Executable Specification Very large block reuse Transactional Memory Intelligent Testbench Design Cost Source: ITRS

Design for Power INNOVATIONS Power Efficiency ITRS Design Productivity Roadmap Expected upcoming Power Management Roadmap Design for Power INNOVATIONS RTL Functional Verif. Tool Suite IC Implementation Tool Set Transaction Level Modeling System Design Automation AMP Parallel Processing Many Core Devel. Tools SMP Parallel Processing Executable Specification Very large block reuse Transactional Memory Intelligent Testbench Power Efficiency Source: ITRS

SOC Modeling by Japan STRJ-WG1 While we had already assembled a Design Technology Roadmap, in 2007 we did quite a few improvements and updates. We start with the “cosmetic” ones – specifically we have made a big effort to make the chapter more concise and consistent, with every section approximately the same size, including its text and its tables. 9

Design / System Drivers 2010*-2011* Plans Design chapter Improvement of design productivity and cost models * Develop “Power Chart” based on STRJ & productivity chart * Ensure 3D / TSV content consistent with other chapters * Improve DFM section, including Design for reliability rows * Overhaul of Verification *, L/C/P sections * System Drivers chapter Update MPU frequency roadmap (flat trend), evaluate impact * Update of SOC-CP and SOC-CS models (driven from TWGs) * Update AMS/RF Driver / fabric with Wireless TWG * More-Than-Moore RF+AMS driver SiP-SoC (based on SoC-P) * Other Cross-TWG and public activity PIDS: increase design-driven requirements definition * 3D/TSV: hold for ACTION * Continue other key interactions: A&P, Interconnect, Test * Incorporate input from 2nd EDA Roadmap Workshop (@DAC)* While we had already assembled a Design Technology Roadmap, in 2007 we did quite a few improvements and updates. We start with the “cosmetic” ones – specifically we have made a big effort to make the chapter more concise and consistent, with every section approximately the same size, including its text and its tables. 10

Design and System Drivers ITRS-iNEMI Domain Space (emulators) Market requirements ITRS (Drivers) Tech requirements Chip level System level *Source: ITRS Design/System Drivers TWG Chairman, Dr. Juan-Antonio Carballo 2011 Roadmap Work in Progress – Do Not Publish! 11

? New System Drivers? At the right pace… Fabrics MPU PE/DSP Memory AMS Is SIP a new fabric ? What application is the right driver for (leading edge) 3D/TSVs ? 2010? 2010? 2007 2006 2006 2006 2010? Fabrics ? MPU SIP PE/DSP We are slowing down in the creation of new drivers, not only because of limited bandwidth, but also because it is not clear that every market will be driving a fundamental parameter in our roadmap – requires some research. As a result: New FPGA driver was suspended (until resource identified) Others (defense) eliminated to synchronize with latest iNEMI Others might be assessed in 2009 (medical, automotive) Memory AMS Markets Medical Automotive Network Office Consumer Portable Consumer Stationary A&D 12

ITRS-iNEMI Domain Space SiP-SoC More-than-Moore Proposal Chip level System level Market requirements Portable emulator Portable consumer driver Tech requirements 1 2 3 RF/AMS Driver Update portable driver Update portable emulator PA Case Study (SoC v. SiP)

An Alternative Driver  Tuner / Demodulator h Inclusion of AMS/RF sub-driver from ITRS AMS driver Tuner-demod case Study Power (SiP) Power (SoC) Additional “rows” for combined analog-digital model Equivalent cost (SoC) Requirement Description Tuner Resolution, operating freqs, power ADC/DAC #bits, order, power, etc. Demodulator /FEC decoder Gain-bandwidth, power Equivalent cost (SiP) Equivalent cost = NRE + non-NRE per-board cost

SOC Modeling by Japan STRJ-WG1 While we had already assembled a Design Technology Roadmap, in 2007 we did quite a few improvements and updates. We start with the “cosmetic” ones – specifically we have made a big effort to make the chapter more concise and consistent, with every section approximately the same size, including its text and its tables. 15

Power-Constrained Frequency Scaling Intrinsic frequency scaling + activity scaling  13% per year  Still exceed 150W in 2015 2009: To meet market needs frequency growth limited  8% per year 2010 (expected): To meet market needs / additional constraints:  flat YTY trend Power < 150W 8% frequency scaling 16

Cross-TWG Interaction: Design-PIDS Device speed scaling: HiPerf CV/I improves by 13%/year Use “headroom” for further power savings? Three devices in the ITRS roadmap High Performance (HP): Highest Ion and Ioff, lowest CV/I Low Operating Power (LOP): Lowest VDD, medium Ion, Ioff and CV/I Low Standby Power (LSTP): Lowest leakage, low Ion, high CV/I Design providing guidance as to targeted ratio of device characteristics Preferred order of dynamic power: LOP < LSTP << HP Preferred order of leakage power: LSTP < LOP << HP Design Group PIDS Group INPUT Ratio of HP : LOP : LSTP R1 R2 R3 Parameters Target design freq.(GHz) Device CV/I Device Ioff FEEDBACK Application driven Technology driven 17

Design / System Drivers 2010*-2011* Plans Design chapter Improvement of design productivity and cost models * Develop “Power Chart” based on STRJ & productivity chart * Ensure 3D / TSV content consistent with other chapters * Improve DFM section, including Design for reliability rows * Overhaul of Verification *, L/C/P sections * System Drivers chapter Update MPU frequency roadmap (flat trend), evaluate impact * Update of SOC-CP and SOC-CS models (driven from TWGs) * Update AMS/RF Driver / fabric with Wireless TWG * More-Than-Moore RF+AMS driver SiP-SoC (based on SoC-P) * Other Cross-TWG and public activity PIDS: increase design-driven requirements definition * 3D/TSV: hold for ACTION * Continue other key interactions: A&P, Interconnect, Test * Incorporate input from 2nd EDA Roadmap Workshop (@DAC)* While we had already assembled a Design Technology Roadmap, in 2007 we did quite a few improvements and updates. We start with the “cosmetic” ones – specifically we have made a big effort to make the chapter more concise and consistent, with every section approximately the same size, including its text and its tables. 18

ITRS-iNEMI MTM SOC/SIP Design/Integration Update of ITRS and iNEMI Portable Drivers h Inclusion of AMS/RF sub-driver from ITRS AMS driver PA Case Study Power (SiP) Power (SoC) Equivalent cost (SoC) Other AMS Equivalent cost (SiP) PA (RF) Equivalent cost = NRE + non-NRE per-board cost

Gaps in EDA (IEEE DAC Roadmap Workshop 2010 Technology EDA nature Metrics 20

Selected Messages 2010 Design productivity continues to be center focus of design technology roadmap, as scaling depends on time to market Accurate design productivity and cost models are key Power consumption has become the key technical parameter that controls feasible semiconductor scaling Power-driven device roadmap, frequency pushed to flat trend More Than Moore has become a necessary component of semiconductor product scaling Mixed SiP-SoC analog-digital drivers need to be roadmapped While we had already assembled a Design Technology Roadmap, in 2007 we did quite a few improvements and updates. We start with the “cosmetic” ones – specifically we have made a big effort to make the chapter more concise and consistent, with every section approximately the same size, including its text and its tables. 21