-1- UC San Diego / VLSI CAD Laboratory A Global-Local Optimization Framework for Simultaneous Multi-Mode Multi-Corner Clock Skew Variation Reduction Kwangsoo Han, Andrew B. Kahng, Jongpil Lee, Jiajia Li and Siddhartha Nath Kwangsoo Han, Andrew B. Kahng, Jongpil Lee, Jiajia Li and Siddhartha Nath VLSI CAD LABORATORY, UC San Diego

-2- Outline Motivation Motivation Related Work Related Work Our Optimization Framework Our Optimization Framework Experimental Setup and Results Experimental Setup and Results Conclusions Conclusions

-3- Motivation Many signoff PVT corners in modern SoCs  “ping-pong” effect == fixing timing issues at one corner leads to timing violation at others Clock skew variation across corners  “ping-pong” effect == fixing timing issues at one corner leads to timing violation at others Our goal: Minimize clock skew variation datapath launch pathcapture path Corner Clock latency Skew LaunchCapture SS, 0.7V, -25°C FF, 1.1V, -25°C Low voltage: gate delay dominates High voltage: wire delay dominates  Skew reversal  Power/area overheads Skew = -0.1 /+0.2 /0.7

-4- Outline Motivation Motivation Related Work Related Work Our Optimization Framework Our Optimization Framework Experimental Setup and Results Experimental Setup and Results Conclusions Conclusions

-5- Related Work Skew minimization at multiple corners [Cho05] perform temperature-aware skew reduction based on an improved DME [Lung10] minimize the worst clock skew across corners with delay correlation factors Skew variation minimization across corners [Restle01] propose two-level non-tree structure, in which mesh is applied at bottom level [Su01] use mesh for top-level of clock network [Rajaram04] insert crosslinks in a clock tree to minimize skew variation Our work: systematic optimization framework for minimization of clock skew variation in clock tree

-6- Skew Variation Reduction Problem At C :Skew i,j C At C’ : Skew i,j C’ i j r r: root; i, j: sinks C’ C’’ i j r C i j r C C’ i j r max … ∑

-7- Outline Motivation Motivation Related Work Related Work Our Optimization Framework Our Optimization Framework Experimental Setup and Results Experimental Setup and Results Conclusions Conclusions

-8- Our Optimization Framework Incremental optimization of a CTS solution Incremental optimization of a CTS solution Perform both global and local optimization Perform both global and local optimization Global optimization uses LP to determine delta delays on arcs Global optimization uses LP to determine delta delays on arcs Local optimization performs iterative local moves Local optimization performs iterative local moves root last-stage buffer sinks Original routed clock tree target buffer After global optimization root After local optimization Routed clock tree database Global Optimization Buffer insertion/removal, routing detour Local Optimization Local moves (e.g., sizing/displacement) Optimized database

-9- Global Optimization: LP Formulate linear program to minimize skew variation  Determine the delta delay on each arc at each corner  Based on LUTs to insert/remove buffer and detour wires Formulate linear program to minimize skew variation  Determine the delta delay on each arc at each corner  Based on LUTs to insert/remove buffer and detour wires Discreteness of buffer delays  ECO feasibility is important Discreteness of buffer delays  ECO feasibility is important  (1) Minimize number of ECO changes  (2) Sweep U for solution with minimum skew variation  (3) Ensure no skew degradation  (4) Maximum clock latency constraint  (1, 5, 6) Improve ECO feasibility

-10- Our Optimization Framework Incremental optimization of a CTS solution Incremental optimization of a CTS solution Perform both global and local optimization Perform both global and local optimization Global optimization use LP to determine delta delays on arcs Global optimization use LP to determine delta delays on arcs Local optimization perform iterative local moves Local optimization perform iterative local moves Routed clock tree database Global Optimization Buffer insertion/removal, routing detour Local Optimization Local moves (e.g., sizing/displacement) Optimized database

-11- Local Optimization: Moves Iterative local moves to minimize skew variation Iterative local moves to minimize skew variation Tree types of local moves Tree types of local moves 1.Displacement {N, S, E, W, NE, NW, SE, SW} by 10μm x one-step sizing 2.Displacement by 10μm x one-step sizing on child buffer 3.Reassign to a new driver (i) at the same level, (ii) within bounding box of 50μm x 50μm 10μm... (1) 10μm... (2)... (3)  Each move is expensive (= legalization, ECO routing, RC extraction, STA)  Each buffer has ~100 candidate moves  Which move is the best? Our solution: learning-based model

-12- Machine Learning-Based Model Predict driver-to-fanout latency change due to local moves Predict driver-to-fanout latency change due to local moves Local move Analytical models Routing: FLUTE, STST Cell delay: Liberty LUTs Wire delay: Elmore, D2M Delta delays Learning-based model Delta delays  Each attempt is a local move  114 buffers  45 candidate moves for each buffer  Learning-based model identifies best moves for more buffers with less #attempts

-13- Outline Motivation Motivation Related Work Related Work Our Optimization Framework Our Optimization Framework Experimental Setup and Results Experimental Setup and Results Conclusions Conclusions

-14- Experimental Setup Technology: foundry 28nm LP Technology: foundry 28nm LP Initial clock tree from Synopsys IC Compiler Initial clock tree from Synopsys IC Compiler Testcases: (a) high-speed application processor, (b) memory controller Testcases: (a) high-speed application processor, (b) memory controller Corners Corners Clock ports In yellow are clock nets/cells and sinks CornerProcessVoltageTemperatureBEOL Apply to which testcase C0SS0.90V-25°CCmax (a), (b) C1SS0.75V-25°CCmax (a), (b) C2FF1.10V125°CCmin (b) C3FF1.32V125°CCmin (a)

-15- Experimental Results (1) Up to 22% reduction on sum of skew variation over all sink pairs Up to 22% reduction on sum of skew variation over all sink pairs No skew degradation at all corners No skew degradation at all corners Negligible area and power overhead Negligible area and power overhead TestcaseFlow Variation (ns) Skew (ps) #Cells Power (mW) Area (μm 2 ) C0C1C2/C3 (a) Original Global-local (b) Original Global-local

-16- Experimental Results (2) Figure shows comparison of skew variation on (a) Figure shows comparison of skew variation on (a) Our optimization significantly reduces the large skew variation between corner pairs Our optimization significantly reduces the large skew variation between corner pairs Corner pair = (C0, C3) Corner pair = (C0, C1) Optimized skew variation (ns) Original skew variation (ns) Optimized skew variation (ns) Original skew variation (ns)

-17- Outline Motivation Motivation Related Work Related Work Our Optimization Framework Our Optimization Framework Experimental Setup and Results Experimental Setup and Results Conclusions Conclusions

-18- Conclusion and Future Works First framework to minimize sum of skew variation over all sink pairs in a clock tree First framework to minimize sum of skew variation over all sink pairs in a clock tree Up to 22% reduction of the sum of skew variation Up to 22% reduction of the sum of skew variation Future works Future works –Study resultant power and area benefits –Model to predict a buffer location for minimum skew over a continuous range of possible locations Thank You!

-19- Backup Slides

-20- Experimental Results (3) Figure shows distribution of skew ratios between C0 and C1 Figure shows distribution of skew ratios between C0 and C1 Our optimization significantly reduces the variation of skew ratios between corner pairs Our optimization significantly reduces the variation of skew ratios between corner pairs μ = = 3.21 μ = = 2.26 Ratio (= skew at C1 / skew at C0) #Sink pairs Original Global-local