Work in progress – Do not publish or distribute 1 Summer Public Conference ORTC 2011 ITRS Alan Allan, Rev 0, 7/13/11

Work in Progress – Do Not Publish 2 1)Unchanged for 2010/11 MPU contacted M1 1)2-year cycle trend through 2013; then 3-year trend to )60f 2 SRAM 6t cell Design Factor 3)175f 2 Logic Gate 4t Design Factor 4)Ongoing - evaluate alignment of nodes with latest M1 industry status and also High Performance/Low Power timing needs 2)Unchanged for 2010/11 Tables: MPU Functions/Chip and Chip Size Models 1)Design TWG Model for Chip Size and Density Model trends – tied to technology cycle timing trends and cell design factors 2)ORTC line item OverHead (OH) area model, includes non-active area 3)Updated for 2010/11 Tables: MPU GLpr, GLph – trends smoothed by PIDS modeling; but close to previous targets 4)Updated for 2010/11 Tables: Vdd Low operating and standby line items from PIDS model track smoothed gate length changes 2010 vs 2011 Renewal ITRS ORTC Technology Trend Pre-Summary

Work in Progress – Do Not Publish 3 5) Updated in ORTC 2011 Tables - DRAM contacted M1: 1)1-year pull-in of M1 and bits/chip trends; 2)no Flattening of DRAM M1 as with Flash Poly** 3)4f2 push out [to 2013]; 6) Updated in ORTC 2011 Tables - Flash Un-contacted Poly: 1)2-year pull-in of Poly; however slower 4-year cycle (0.5x per 8yrs) trend to 2020/10nm; then 3-year trend to 2022/8nm; ** then Flat Poly after 2022/8nm; 2)and 3bits/cell extended to 2018; 4bits/cell delay to )Updated in ORTC 2011 Tables - DRAM Bits/Chip and Chip Size Model: 1)3-year generation Moores Law bits/chip doubling cycle target (1-2yr delay for smaller chip sizes) 8)Updated in ORTC 2011 Tables - Flash Bits/Chip and Chip Size Model: 1)2-year generation Moores Law bits/chip doubling cycle target (after 1-yr acceleration for higher densities sooner); 2)New 3D layers Models vs. relaxed half-pitch tradeoffs are now included in the 2011 Renewal 2010 vs 2011 Renewal ITRS ORTC Technology Trend Pre-Summary (cont.)

Work in Progress – Do Not Publish 4 9)Updated in ORTC 2011 Tables - ORTC Table 5 - Litho # of Mask layers MPU, DRAM, 9)Flash Survey inputs Updated 10)Also IC Knowledge (ICK) model contribution to extend mask levels range 10)Unchanged for IRC 450mm Position: 1)Timing Status 1)Consortia work underway 2)IDM and Foundry Pilot lines: ; 3)Production: )ISMI making good progress on 450mm program activities to meet the ITRS Timing 3)Europe momentum building - EEMI status reviewed with IRC in Potsdam 4)FI TWG will extend 300mm wafer generation in parallel line item header with 450mm; 1)Including Technology upgrade assumptions through end of roadmap 2)Assuming compatibility of 300mm productivity extensions into the 450mm generation ; 5)Utilizing a new ITRS-based ICK Strategic commercial model, SEMATECH has developed 300mm and 450mm Range Scenarios for silicon and equipment demand 11)Updated in More than Moore white paper online at 1)New Moores Law and More Graphic update included in 2011 ITRS Executive Summary 2)MtM Workshop completed in Potsdam, GE, in April and reviewed at Summer ITRS meeting 3)New MEMS TWG and Chapter added to 2011 ITRS 2010 vs 2011 Renewal ITRS ORTC Technology Trend Pre-Summary (cont.)

Work in Progress – Do Not Publish –IRC Equivalent Scaling Graphic Update Included in 2011 Update: Parallel bulk and SOI pathways; and Clarification of gate mobility materials pathway Pull-in placement of MuGFET Timing (taking into account multiple manufacturers) –PIDS and FEP Memory Survey Proposal Updates Possible additional acceleration –FEP and Design and System Drivers Logic Monitor Monitor MPU and Leading Edge Logic technology trends –A&P/Design Power Model Possible proposals for Power Dissipation "hot spot" model rather than chip area basis –PIDS/Design Max On-chip Frequency vs Intrinsic Modeling Included in 2011 Update: New Max Chip Frequency trends (reset to 3.6Ghz/2010 plus 4% CAGR trend) TBD PIDS Intrinsic Transistor and Ring Oscillator model Changes to 8% [from unchanged % trend] PIDS Updates include MASTAR static modeling near-term and TCAD dynamic long-term modeling Also equivalent scaling tradeoffs (FDSOI, MuGFET, III-V/Ge) with dimensional scaling –YE Defect Density Modeling New ORTC Defect Density model work moved to 2012 Update due to loss of modeling resources 5 Technology Pacing Cross-TWG Study Group (CTSG) work preparation for 2012 Update: 2010 vs 2011 Renewal ITRS ORTC Technology Trend Pre-Summary (cont.)

Updated Flash Poly Definition DRAM and MPU/ASIC Unchanged 2011 Definition of the Half Pitch – New 2010 Poly Definition [Note: The ITRS does not utilize any single-product node designation reference; Flash Poly and DRAM M1 half-pitch are still litho drivers; however, other product technology trends may be drivers on individual TWG tables] Source: 2009 ITRS - Exec. Summary Fig 1 Poly Pitch Typical flash Un-contacted Poly FLASH Poly Silicon ½ Pitch = Flash Poly Pitch/ Lines Lines Metal Pitch Typical DRAM/MPU/ASIC Metal Bit Line DRAM ½ Pitch = DRAM Metal Pitch/2 MPU/ASIC M1 ½ Pitch = MPU/ASIC M1 Pitch/2 Rev 8, 07/08/11 Status Revision Work in Progress – Do Not Publish!

7 Production Ramp-up Model and Technology/Cycle Timing Months Alpha Tool DevelopmentProduction Beta Tool Production Tool First Conf. Papers First Two Companies Reaching Production K 20K 200K Additional Lead-time: ERD/ERM Research and PIDS Transfer Volume (Wafers/Month) Production Ramp-up Model and Technology Cycle Timing Source: 2009 ITRS - Exec. Summary Fig 2a *Examples: 25Kwspm ~= 280mm2 140mm2 100mm2 70mm WAS 2011 Unchanged

Work in Progress – Do Not Publish! 8 ERD/ERM Long-Range R&D and PIDS Transfer Timing Model Technology Cycle Timing [Example: MOSFET High-mobility Channel Replacement Materials] Source: 2009 ITRS - Executive Summary Fig 2b Months Alpha Tool Development Production Beta Tool Product Tool Volume (Wafers/Month) K 20K 200K Research Transfer to PIDS/FEP (96-72mo Leadtime) First Tech. Conf. Device Papers Up to ~12yrs Prior to Product Hi- Example: 1 st 2 Cos Reach Product First Tech. Conf. Circuits Papers Up to ~ 5yrs Prior to Product 2010 WAS 2011 Unchanged

Work in Progress – Do Not Publish! ITRS Near-Term: [new PIDS 2011 Roadmap Flash and DRAM Trend Driver Proposals]

Work in Progress – Do Not Publish! ITRS Long-Term: [new PIDS 2011 Roadmap Flash and DRAM Trend Driver Proposals]

Work in Progress – Do Not Publish 11 16nm Near-TermLong-Term Source: 2009 ITRS - Executive Summary Fig 7a 2010 ITRS Summary Figure 5a Figure 5a DRAM and Flash Memory Half Pitch Trends

Work in Progress – Do Not Publish 12 Source: 2009 ITRS - Executive Summary Fig 7a 2010 ITRS Summary Figure 2 – With Updated 2011 Flash Scenario 2 from 2011 ITRS Kickoff Figure 2 ORTC Table 1 Graphical Trends (including overlay of PIDS update proposals for 2011 ITRS effort) 16nm Near-TermLong-Term PIDS DRAM Projection ~1-yr pull-in 42nm M1 to 2010 (2 cos); Then 3-yr cycle to 2024/8nm; 2019: PIDS Flash 4 bits/cell push-out Memory PIDS 2011 Proposals 2013: PIDS DRAM 4f2 Design Factor bits/cell push-out PIDS 2011 Sc 2: 2010/24[23.84]nm; Then 4yr cycle* to 2020/10nm; Then 3-yr cycle to 2022/8nm; Then flat/8nm to 2026: 4yr cycle = /yr: 2010/23.84nm 2011/21.86nm 2012/ nm 2016/14.17nm 2020/ nm 2022->26/7.95nm 2011 ITRS: D - 8 layers 3D layers PIDS 3D Flash : 26nm Poly half-pitch /32; Then /28; Then /24 Then /18nm ~5.5-yr Cycle ? [Including Final PIDS 2011 ITRS Proposal Revision for 2011 ITRS Work] Long-Term 11

Work in Progress – Do Not Publish! 13 Flash (NAND) Product Size Generations 2009 ITRS Renewal: PIDS Flash Size: ??? 4x/4-5yrsWAS'09 16G64G256G1T Interim Generations: ???2007 ??? 4x/4-5yrsWAS'09 32G128G512G2T 5yrs4yrs 2011 ITRS Renewal (PIDS 2010 Update Proposal): PIDS Flash Size: x/4-5yrsWAS'09 16G 64G 256G 1T 4x/4-5yrsIS'11 64G 256G 1T Interim Generations: x/4-5yrsWAS'09 32G 128G 512G 2T n/a 4x/4-5yrsIS'11 32G 128G 512G 2T 4yrs 5yrs 4yrs ??yrs Poly uncontacted half pitch = 1-year pull-in 2010/23.8nm; then 4-year cycle to 2020; then 3-year cycle; then flat at 8nm/ Product memory size: 2 years cycle for introducing 2x product; pull-ins: 1-yr for 32G, 64G, 512G, 1T, 2T; and 2-year for 128G, 256G 128Gbit chip will be available in NAND Cell Array Efficiency unchanged from 56% in ITRS 2010

Work in Progress – Do Not Publish! 14 DRAM Product Size Generations 2009/10 ITRS Renewal: PIDS DRAM Size: x/6yrs G16G64G WAS'09/10 4G16G64G Interim Generations: x/5-6yrs G8G32G 4x/6yrs WAS'09/10 2G8G32G 5yrs6yrs 2011 ITRS Renewal (PIDS 2010 Update Proposal): PIDS DRAM Size: x/6yrs WAS'09/10 4G 16G 64Gn/a 4x/7yrs IS'11 4G 16G 64G Interim Generations: x/6yrs WAS'09/10 2G 8G 32G 4x/6yrs IS'11 2G 8G 32G 6yrs 7yrs? DRAM M1 half pitch = 1-year pull-in; then 3-year cycle to 2026 DRAM Product Size; Keep ITRS 2009: 2G, 4G, 8G; but 16G delay 1 yr to 2017; add 64G/2025 DRAM Cell size factor: 4F2 cell will be available in Delay 2years from ITRS2009/10 DRAM Cell Array Efficiency = 59%; versus 56.1% in ITRS 2010

15 16nm Near-TermLong-Term 2010 ITRS Summary Figure 5b Figure 5b MPU/high-performance ASIC Half Pitch and Gate Length Trends [ Unchanged from 2009 ITRS ] 2009/2010 ITRS versions WAS versus IS/Unchanged (except extend to new end period): 2011 ITRS: Work in Progress – Do Not Publish!

16 16nm Near-TermLong-Term 2010 ITRS Summary Figure 5b Figure 5b MPU/high-performance ASIC Half Pitch and Gate Length Trends [ Unchanged from 2009 ITRS ] 2009/2010 ITRS versions WAS versus IS/Unchanged (except extend to new end period): 2011 ITRS: Work in Progress – Do Not Publish! Equiv. Scaling Trade- off Strain HK/MG MuG-FET Hi-u,(tbd) ITRS 1999 P. Gargini Equivalent Scaling Concept FDSOI PDSOI IS: 2011 ITRS: Long-Term ITRS: Extend M1; &GLpr; to 2026 on 3-year Cycle GLph versus M1 in analyzing implications 1995->2015 Nodes (10) ITRS M1 hp nm ITRS GLph 90nm-45nm

Work in Progress – Do Not Publish! 17 Updated Proposal - for 2011 work Metal High k Gate-stack material Bulk FDSOI Multi-gate (on bulk or SOI) Structure (electrostatic control) Channel material Metal High k 2nd generation Si + Stress S D High-µ InGaAs; Ge S D PDSOI Metal High k nth generation Possible Delay Possible Pull -in 17 See also PIDS, FEP, ERD, and ERM chapters text and tables for additional detail) 68nm45nm 32nm22nm 16nm 2009 IS ITRS DRAM M1 : 2009 ITRS MPU/hpASIC M1 : 76nm 65nm 54nm 45nm 38nm 32nm 27nm 19nm 13nm MPU/hpASIC Node: 45nm 32nm 22nm 16nm 11nm 8nm 2009 ITRS hi-perf GLph : 32nm 29nm 29nm 27nm 24nm 22nm 20nm 15nm 12nm 2009 ITRS hi-perf GLpr : 54nm 47nm 47nm 41nm 35nm 31nm 28nm 20nm 14nm 45nm32nm 22nm16nm11nm 2009 IS ITRS Flash Poly : 54nm 2009 ITWG Table Timing: = Additional timing movement considerations for 2011 ITRS work 2010 ITRS Summary Figure 3 Equivalent Scaling Roadmap Figure 3 ORTC Table 1 Graphical Trends (including overlay of 2009 industry logic nodes and ITRS trends for comparison) [ PIDS/FEP/Design HP/LOP/LSTP Sub-Team Transistor Modeling Work Underway ] Need Proposals - for 2012 Update work; Plus 2011 Text & Exec. Summary Topic

Work in Progress – Do Not Publish ORTC Table 4: Design TWG Model for On- Chip Frequency –Lower model starting point 2010/3.6Ghz –4% growth rate through 2026 –*Unchanged 2011 ITRS 13% PIDS target model Intrinsic Transistor Frequency Growth; –*However, proposal for 2012 ITRS 8% PIDS target model Intrinsic Transistor Growth (work preparation in 2011) 18 Table ORTC-4 Performance and Packaged Chips Trends Year of Production Chip Frequency (MHz) WAS On-chip local clock [2] Design /IS On-chip local clock [2] Ghz

Work in Progress – Do Not Publish! 19 CV/I (ps) Year of Production Ramp 1/(CV/I) Ring Oscillator (invertors) 101 stages; 1001, etc. FO 1 (capacitance example.1pf) FO 4 (capacitance example.4pf) PIDS Table 2: CV/I – ITRS Unchanged 1/(CV/I )(Ghz) Year of Production Ramp 1/(CV/I) Ring Oscillator (invertors) 101 stages; 1001, etc. FO 1 (capacitance example.1pf) FO 4 (capacitance example.4pf) ITRS PIDS ITRS CV/I Trends vs Possible 2012 ITRS MUG-FET Pull-In What if proposal

Work in Progress – Do Not Publish! 20 CV/I (ps) Year of Production Ramp PIDS Table 2: CV/I – ITRS Unchanged 1/(CV/I )(Ghz) Year of Production Ramp Note: 1/(CV/I) frequency is reduced by a factor of 1/22.4 in a PIDS model of a Ring Oscillator (inverter chain) 101 stages; 1001 stages, etc.; FO 1 (capacitance example.1pf); FO 4 (capacitance example.4pf) PIDS ITRS CV/I Trends vs Possible 2012 ITRS MUG-FET Pull-In What if proposal 1/(CV/I) (Ghz) ~ +13% CAGR; from: CV/I (ps) ~ -11% CAGR 1/(CV/I) (Ghz) ~ +13% CAGR; from: CV/I (ps) ~ -11% CAGR Note: 1/(CV/I) frequency is reduced by a factor of 1/22.4 in a PIDS model of a Ring Oscillator (inverter chain) 101 stages; 1001 stages, etc.; FO 1 (capacitance example.1pf); FO 4 (capacitance example.4pf)

21 Source: ITRS Test TWG compilation, ca 4Q 2010 ITRS 2011 IS Past Future PIDS/FEP 1/(CV/I) WAS: 13% CAGR (~2x/5.5yrs) 2011 Proposal by Design TWG: 1/(CV/I) = 8% CAGR (~2x/9yrs) ORTC Table 4: On-Chip Local Clock Frequency: 2011 Proposal by Design TWG: 4% CAGR (~2x/18yrs), Trend begins at 2010: High [not included in ORTC]: 5.5Ghz [special cooling] ORTC: On-Chip Freq: 3.6Ghz On-Chip Clock Frequency: Performance Improvement tradeoffs provided by Equivalent Scaling Including Design Alternatives: -Multi-Core Architecture -Memory Architecture -Software Power Management -Etc. Work in Progress – Do Not Publish! ORTC Table 4: On Chip Local Clock Frequency GOLD Trend Historical Trend: 26% CAGR (~2x/3yrs) Historical Trend: 39% CAGR (~2x/2yrs) PIDS/FEP 2012 Update Proposal PIDS/FEP CV/I WAS 2007: 1/(CV/I) = from 18% to 13% CAGR (~2x/5.5yrs) 2007 Proposal by Design TWG: On-Chip Freq. = from 18% to 8% CAGR (~2x/9yrs) PIDS/FEP Ring Oscillator Model 101 invertor stages With equivalent Fan-out 4 Capacitance load; Results in Frequency of ~1/22 x 1/(CV/I) at 13% CAGR (~2x/5.5yrs) Design Hroom 1/22.4 PIDS/FEP 1/(CV/I) at 13% CAGR (~2x/5.5yrs) PIDS/FEP 1/(CV/I) at 8% CAGR (~2x/9yrs)

Work in Progress – Do Not Publish ORTC Table 5 Update: Litho TWG IS model for Mask Count –MPU survey-based, mask counts peak 2014/(54 masks peak) EUV expected 2015 –DRAM referenced to MPU, mask counts peak 2012/(41 masks peak) EUV expected 2013 –Flash survey-based, mask counts peak 2012/(43 masks peak) EUV expected 2013 –Sidewall image transfer technology IEDM papers should be evaluated –Table 5 also includes NEW IC Knowledge (ICK) modeled comparison targeting ITRS 2011 Litho EUV timing; but extended out through 2024 using ITRS ( ) assumptions –Limited YE Defect Density modeling resources requires delay of update response to

Work in Progress – Do Not Publish 23 SEMATECH Survey ITRS 2011 IS: With MPU EUV in 2015; DRAM & Flash in 2013 Litho 2011 Survey vs ICK 2011 ITRS-based* Model [*extended to 2024 based on ITRS ]

Work in Progress – Do Not Publish 24 Litho 2011 Survey vs ICK 2011 ITRS-based* Model [*extended to 2024 based on ITRS ] ICK Strategic Model* *Based on ITRS v With MPU EUV in 2015; DRAM & Flash EUV in 2013 Flash Charge Trap in 2012; Multi-layer 3D begins 2016 MPU Delay EUV to 2017 Backup:

Work in Progress – Do Not Publish 25 Litho 2011 Survey IS vs ICK-based* 2012 ITRS Model Proposal [*extended to 2024 based on ITRS ; then smoothed and extrapolated ] Backup: ITRS 2012 Update Proposal: MPU: DRAM: Flash: ITRS 2011 SEMATECH Survey-based IS: MPU ; DRAM ; Flash vs. ICK-based proposal With MPU EUV in 2015; DRAM & Flash EUV in 2013 ITRS 2012 Update (ICK-based) Proposal: MPU: DRAM: Flash: Flash Charge Trap in 2012; Multi-layer 3D begins 2016

Work in Progress – Do Not Publish! ITWG Table Timing: nm45nm 32nm22nm 16nm 2009 IS ITRS DRAM M1 : 2009 ITRS MPU/hpASIC M1 : 76nm 65nm 54nm 45nm 38nm 32nm 27nm 19nm 13nm MPU/hpASIC Node: 45nm 32nm 22nm 16nm 11nm 8nm 2009 ITRS hi-perf GLph : 32nm 29nm 29nm 27nm 24nm 22nm 20nm 15nm 12nm 2009 ITRS hi-perf GLpr : 54nm 47nm 47nm 41nm 35nm 31nm 28nm 20nm 14nm 45nm32nm 22nm16nm 11nm 2009 IS ITRS Flash Poly : 54nm Volume Years Alpha Tool Beta Tool Tools for Pilot line 32nm (extendable to 22nm) M1 half-pitch capable Beta tools by end of 2011 Consortium Pilot Line Manufacturing 22nm (extendable to 16nm) M1 half- pitch capable tools Development Production 450mm 32nm M1 half-pitch Pilot Line Ramp Beta Tool Production Tool 450mm Production Ramp-up Model [ 2009 Figure 2c A Typical Wafer Generation Pilot Line and Production Ramp Curve ] Source: 2009 ITRS - Executive Summary Fig 2c 450mm Production Ramp-up Model [ 2009 ITRS Figure 2c A Typical Wafer Generation Pilot Line and Production Ramp Curve ] Versus Node/actual contacted M1 and un-contacted Poly Half-Pitch alignment nm nm nm nm nm nm Unchg 11nm nm nm nm 2009/10 WAS 2011 Unchanged [ORTC DRAM, Flash M1 and Poly Half-Pitch timing changes per below] 20xx xxnm 20xx xxnm *Note: At ITRS/Europe, the IRC approved continuing the ITRS 450mm Timing Graphic unchanged for use in the 2011 ITRS Roadmap guidance.

Work in Progress – Do Not Publish! 27 Backup: 1)Moores Law and More Graphic Update 2)4Q10 SICAS Technology Capacity Demand Tracking Update 3)Nodes vs MPU/ASIC Technology Trends 4)ORTC Table 4 Design On-chip Frequecy vs History and Nodes 5)ORTC Table 6 PIDS Gate Length vs. HP, LOP, LSTP Vdd 6)Litho Survey #Mask Levels Survey/Technology Timing Alignment 7)ORTC Table 5 #Mask Levels and Notes 8)FEP Logic Status Monitor 9)IMEC FinFET SRAM Cell Articlewww.electroiq.com

Work in Progress – Do Not Publish 28 More than Moore: Diversification More Moore: Miniaturization Combining SoC and SiP: Higher Value Systems Baseline CMOS: CPU, Memory, Logic Biochips Sensors Actuators HV Power Analog/RFPassives 130nm 90nm 65nm 45nm 32nm 22nm 16 nm. V Information Processing Digital content System-on-chip (SoC) Beyond CMOS Interacting with people and environment Non-digital content System-in-package (SiP) 2010 ITRS Summary Figure 4 Figure 4 The Concept of Moores Law and More 2010/2011 Unchanged

Work in Progress – Do Not Publish! 29 >0.7 m m m m m m <0.08 m m <0.06 m Technology Cycle Timing Compared to Actual Wafer Production Technology Capacity Distribution * Note: The wafer production capacity data are plotted from the SICAS* 4Q data for each year, except 2Q data for The width of each of the production capacity bars corresponds to the MOS IC production start silicon area for that range of the feature size (y-axis). Data are based upon capacity if fully utilized. Year Feature Size (Half Pitch) ( m) 2008/09 ITRS: 2.5-Year Ave Cycle for DRAM 2-Year DRAM Cycle 3-Year DRAM Cycle ; 2-year Cycle Flash and MPU 3-Year Cycle = 2003/04 ITRS DRAM Contacted M1 Half-Pitch Actual = 2007/09 ITRS DRAM Contacted M1 Half-Pitch Target = 2009 ITRS Flash Un-contacted Poly Half Pitch Target = 2009 ITRS MPU/hpASIC Contacted M1 Half-Pitch Target 3-Year Cycle After 2010 for Flash; after 2013 For MPU Source: 2009 ITRS - Executive Summary Fig 3 4Q09 SICAS Update Proposal From Furukawa-san/Japan To IRC 3/28/10 (modified by AA) Year