Test and Test Equipment December 2010 Makuhari Meese, Japan Roger Barth 1

2010 Test Team Jerry Mcbride Jody Van Horn Kazumi Hatayama Ken Lanier Ken Taoka Ken-ichi Anzou Khushru Chhor Masaaki Namba Masahiro Kanase Michio Maekawa Mike Bienek Mike Peng Li Mike Rodgers Paul Roddy Peter Maxwell Phil Nigh Prasad Mantri Rene Segers Rob Aitken Roger Barth Sanjiv Taneja Satoru Takeda Sejang Oh Shawn Fetterolf Shoji Iwasaki Stefan Eichenberger Steve Comen Steve Tilden Steven Slupsky Takairo Nagata Takuya Kobayashi Tetsuo Tada Ulrich Schoettmer Wendy Chen Yasuo Sato Yervant Zorian Yi Cai Akitoshi Nishimura Amit Majumdar Anne Gattiker Atul Goel Bill Price Burnie West Calvin Cheung Chris Portelli-Hale Dave Armstrong Dennis Conti Erik Volkerink Francois-Fabien Ferhani Frank Poehl Hirofumi Tsuboshita Hiroki Ikeda Hisao Horibe 2 2

2009 Changes DFT Test Cost Adaptive Test Prober Probecard Handler Test data compression and test time potential solutions identified Major rewrite completed of the Design Chapter DFT section Test Cost Test cost survey completed that quantifies industry view Test parallelism dependency by device type modified based on I/O count Adaptive Test New chapter section shows necessity for adaptive test to lower cost Prober Complete redo of prober table to address parallelism and power Probecard LCD display driver probe added as driver Handler Added 10-50 Watt handler category Test Sockets Socket BW limitations on current sockets New future contacting solutions are required 3 3

2010 Drivers Device trends Test process complexity Unchanged Revised New Drop Device trends Increasing device interface bandwidth and data rates Increasing device integration (SoC, SiP, MCP, 3D packaging) Integration of emerging and non-digital CMOS technologies Device characteristics beyond the deterministic stimulus/response model Fault Tolerant architectures and protocols 3 Dimensional silicon - multi-die and Multi-layer Multiple Power modes and Multiple time domains Complex package electrical and mechanical characteristics Test process complexity Adaptive test and Feedback data Concurrent test within a DUT Maintaining unit level test traceability Device customization / configuration during the test process “Distributed test” to maintain cost scaling 4 4

Drivers Economic Scaling of Test Physical limits of packaged test parallelism Test data volume Managing interface hardware and (test) socket costs Multiple Insertions and System test Effective limit for speed difference of HVM ATE versus DUT Trade-off between the cost of test and the cost of quality Unchanged Revised New Drop 5 5

2010 Difficult Challenges Test for yield learning Unchanged Revised New Drop Test for yield learning Critically essential for fab process and device learning below optical device dimensions Detecting Systemic Defects Testing for local non-uniformities, not just hard defects Detecting symptoms and effects of line width variations, finite dopant distributions, systemic process defects Screening for reliability Effectiveness and Implementation of burn-in, IDDQ, and Vstress testing Detection of erratic, non deterministic, and intermittent device behavior 6 6

2010 Difficult Challenges Potential yield losses Unchanged Revised New Drop Potential yield losses Tester inaccuracies (timing, voltage, current, temperature control, etc) Over testing (e.g., delay faults on non-functional paths) Mechanical damage during the testing process Defects in test-only circuitry or spec failures in a test mode e.g., BIST, power, noise Some IDDQ-only failures Faulty repairs of normally repairable circuits Decisions made on overly aggressive statistical post-processing 7 7

No 2010 Changes 2011 update planned Test Cost Components 8 8

Test Cost Survey No 2010 Changes 2011 update planned 2009 Survey to determine key factors & metrics Test Cost Metrics Cost per unit Percent of total Product Cost Cost per second Cost per megabit (memory) Metrics Not used Cost per transistor Capital expenditures Major Test Cost Drivers ATE capital Interface hardware Test program development Test Time and Coverage Current Methods of controlling cost Test Parallelism Reduced Pin interfaces Structural Test & Scan DFT and BIST Concurrent test Future Methods of controlling cost Wafer-level at-speed testing Advanced embedded instruments Adaptive Test New contacting technologies Build-in Fault Tolerance 9

Adaptive Test New in 2009 Modify testing based on analysis of previous results Real-time Near-time Off-line Benefits Higher Quality Fast Test Time Reduction Lower cost Fast yield learning Requires data infrastructure Database Analysis tools  Confidence Implementation is evolving Multiple learning steps Delaying won’t ease task

Test Parallelism Update Soc, Low Performance Logic, commodity DRAM and Commodity Flash unchanged 11 11

SoC Updates Fault models pulled in Bridging faults to 2011 Full ATE standardized interface delayed from 2013 to 2015 DFT based defect analysis has slightly extended life 12 12

Logic Update Changes driven by ORTC and Design TWG updates 13

Memory Update NAND Density update driven by ORTC change I/O width & Channels dropped 14

RF Update Increase in short term Carrier Frequency for 2010 Limited need for 12 GHz requirements… 20GHz appears to be small volume as compared to other devices…may be lack of developed instrumentation Target is now 60+ GHz (personal networks and SR radar) 15 15

Probing Technology Update 2011 memory roadmap will separate DRAM and Flash in table Low contact force probing process requirement added to roadmap 16 16

3D Devices Multiple die system Sub-systems designed to operate and be assembled together Process optimized for contents of each die Logic, DRAM, NVM, Analog Connection by potentially 1000’s of TSVs (Thru Silicon Via’s) Design, Interconnect, Assembly and Test, PIDS and FEP problem DFT Requirements Testability of each die Vias cannot be probed due to ESD issues N+ die test methodology a possibility as die added, not recommended Final 3D Packaged test void

TSV Test Strategy New for 2010 Strong Recommendations Needs Trends Can’t (and don’t) touch the TSVs. Alternative test pads with ESD protection are ok (analog, power, digital) Use Boundary scan test for access Design independently testable die Cannot require resources from other die for test Need not operate in mission mode Design low resistance TSVs TSV geometry and parametrics are not be the critical technology limiter Needs Thermal considerations needed for scan after stack Optimal functional / performance / system test Possible benefit to self Speed Test (SST) thru TSV loop (post stack) Trends System test / validation much more important in the future with TSVs. The die stack is a system. 18 18

Test Time Reduction Potential Solutions Required test time reduction is driven by SoC Assumes increasing design complexity and transistor count will not increase test time 19 19

DFT Compression Potential Solutions Development is necessary to get very high levels of data compression Demonstrated techniques are just approaching 1000x 100k data compression necessary out in time…no clear path yet! 20 20

Jitter Test Critical for HS High Speed Interfaces Limit? Jitter Test Critical for HS Interfaces Test Sockets are not able to support controlled impedance contacts at >15 GT/s Bit bandwidth increasing… Physical limit? Test limit?

Summary of 2010 table (trend) Changes Major update of Device Trends and Challenges Minor adjustments to tables Test parallelism SoC Logic (ORTC driven) Memory (ORTC driven) RF Probing Technology Refinement of TSV testing strategy 22 22

2011 Plans Further definition of 3D Silicon test and DFT requirements Investigate potential methods for data volume reduction Probing and Contacting of high speed Digital and Analog Probing of very thin wafers Die level tracking proposal Cost model update 23

Backup

Test Topics (Chapter Sections) Key Drivers, Difficult Challenges, Opportunities Test for Yield Learning Cost of Test Adaptive Test DFT SoC and SiP Logic Memory – DRAM, NOR, NAND, Embedded Analog, RF and Mixed Signal Reliability Technology Burn-in Mechanical: Handlers and Probers Interface: Probecards and Test Sockets Specialty Devices – MEMS, Image Sensors, Accelerometers 25 25

SoC – Consumer Logic > 1000 cores by 2020 Per core DFT FLASH RAM HS Serial MPU Analog I/O and Logic DSP RF > 1000 cores by 2020 MPU / logic Memory Analog / RF HS serial Per core DFT SoC test challenges Management of per core DFT Standardization of core “wrappers” IEEE 1500 core test IEEE P1687 JTAG chip-test High Data Compression (>100) Amount Of DFT SoC Complexity

System in Package (SiP) Target is low power devices Challenges High yield with low test cost Standardized test strategy for mini-systems Potential test solutions Design for die, debug and system test Per die BIST KGD with minimal post test “KGD” defined as Functional and Structural good? Simple Complex

From Assembly and packaging TWG Typical SiP in 2010 From Assembly and packaging TWG TSV Mold resin thickness on top of die: 0.10 mm 0.025mm ●　●　　　　　　　　　　　　　　　　　　　　●　● 1.0 Substrate thickness: 0.16 ●　●　●　●　　　　　　　　　　●　●　●　● Die attach thickness 　0.015 Ball pitch: 0.8 mm Ball diameter: 0.4 mm Embedded 28

Fault Tolerant Devices “Bad but Good” Many future devices will be Fault Tolerant “Adapt or Repair” Homogeneous multi-core device…not all cores need be good Identify with “Smart kernel” or continuous test… …Ignore the bad core …Fix (run slower or tailor operations) Memory Allow or correct bad bits / blocks Background memory checker Wear leveling Image sensors without the “perfect” image What is perfect? Core No 2010 Changes

Prober Characteristics Many changes / additions from 2008 tables Probe card dimensions Test head weight Temperature accuracy 450mm wafer support Chuck leakage Planarity Etc. Solutions exist until 2014 2009 2008 DRIVERS Full wafer test Device Power

Image sensor structure cross section Specialty Devices LCD drivers Form factor of 30mm x 1.5mm Long bond pads on 20um centers Image sensors Micro lens check with pupil test 3 axis MEMS Accelerometer Consumer drop/rotate applications Probing pad 10x120 um Image sensor structure cross section

Thanks!