ITRS Public Conference Emerging Research Devices 2013 ERD Chapter Preparation An Chen, Shamik Das, Victor Zhirnov and Jim Hutchby

Emerging Research Devices Working Group Hiro Akinaga AIST Tetsuya Asai Hokkaido U. Yuji Awano Keio U. George Bourianoff Intel Michel Brillouet CEA/LETI John Carruthers PSU Ralph Cavin SRC Chorn-Ping Chang AMAT An Chen GLFOUNDRIES U-In Chung Samsung Byung Jin Cho KAIST Sung Woong Chung Hynix Luigi Colombo TI Shamik Das Mitre Antoine Khoueir Seagate Bob Doering TI Tetsuo Endoh Tohoku U. Bob Fontana IBM Paul Franzon NCSU Akira Fujiwara NTT Mike Garner Stanford Dan Hammerstrom PSU Wilfried Haensch IBM Tsuyoshi Hasegawa NIMS Shigenori Hayashi Panosonic Dan Herr UNCG/JSNN Toshiro Hiramoto U. Tokyo Matsuo Hidaka ISTEK Jim Hutchby SRC Adrian Ionescu EPFL Kiyoshi Kawabata Renesas Tech Seiichiro Kawamura JST Suhwan Kim Seoul Nation U Hyoungjoon Kim Samsung Atsuhiro Kinoshita Toshiba Dae-Hong Ko Yonsei U. Mark Kryder INSIC Franz Kreupl Tech. U. Munich Zoran Krivokapic GLOBALFOUNDRIES Kee-Won Kwon Seong Kyun Kwan U. Jong-Ho Lee Hanyang U. Thomas Liew ASTAR DSI Lou Lome IDA Matthew Marinella SNL Hiroshi Mizuta U. Southampton Kwok Ng SRC Fumiyuki Nihei NEC Dmitri Nikonov Intel Kei Noda Kyoto U. Ferdinand Peper NICT Er-Xuan Ping AMAT Yaw Obeng NIST Yutaka Ohno Nagoya U. Dave Roberts Nantero Shintaro Sato Fujitsu Labs Barry Schechtman INSIC Sadas Shankar Intel Takahiro Shinada AIST Masayuki Shirane U. Tokyo Kaushal Singh AMAT Satoshi Sugahara Tokyo Tech Shin-ichi Takagi U. Tokyo Ken Uchida Keio U. Thomas Vogelsang Rambus Yasuo Wada Toyo U. Rainer Waser RWTH A Franz Widershoven NXP Jeff Welser NRI/IBM Philip Wong Stanford U. Dirk Wouters IMEC Kojiro Yagami Sony David Yeh SRC/TI Hiroaki Yoda Toshiba In-K Yoo SAIT Victor Zhirnov SRC

Evolution of Extended CMOS Elements More Than Moore Existing technologies New technologies Beyond CMOS year

Assessing Emerging Research -- 2013 ERD Chapter Assessing Emerging Research -- Memory Devices Logic Devices More-than-Moore Devices Architectures Benchmarking Emerging Devices

Key Messages Emerging Research Memory: Emerging Research Logic: Remove Nanomechanical Memory from ERD technology table Recommend close tracking of RRAM by PIDS Workshops on Memory Select Devices and Storage Class Memory completed Quantitative data for roadmapping Implement multilevel energy analysis for different memory technologies Emerging Research Logic: Emerging logic device workshop completed: device maturity evaluation Recommend close tracking of p-III-V, n-Ge, nanowire FET, TFET by PIDS Add emerging interconnect discussions in ERD Together with RFAMS, mapping ERD devices for analog/RF applications More-than-Moore Section: New entry will be added: on-chip energy harvesting devices Develop appropriate figure-of-merits for emerging devices in MtM applications Emerging Architectures: Plan workshop on emerging research architectures (Dec. 8, San Francisco, CA) Add emerging memory interface for Storage Class Memory

Cross-TWIG Interactions Discussions with PIDS on emerging research memory and logic devices for close tracking of maturing technologies RRAM Nanowire FET, Tunnel FET, p-III-V, n-Ge Formed a taskforce with RF/AMS for evaluation of ERD devices for RF/Analog application Envisioned outcome: a parametrization table in ERD MtM section Formed a taskforce with Interconnects for exploring emerging interconnects solutions for emerging research devices Envisioned outcome: expanding ERD tables to include emerging interconnect solutions Initiated discussion with Design and AP on exploring circuit design and application space for ERD

2012 ERD Workshops (Co-sponsored by NSF) Workshop on assessment of options for emerging memory select devices Noorwijk, the Netherlands, April 22, 2012 Status: Completed and report finished Workshop on emerging architectures for storage class memory   Monterey, CA, July 8, 2012 Workshop on emerging research logic devices  Bordeaux, France, September 21, 2012 (ESSDERC-linked) Status: Completed and report in progress Workshop on emerging research architectures San Francisco, CA, Dec 8, 2012 (IEDM-linked) Status: Agenda completed

Select Device Workshop Outcome Workshop presentations will be put on ITRS website Workshop results are summarized in a report (finished) Several take-away messages There are several categories of memory select devices depending on memory device type and applications e.g. RRAM or PCM; embedded vs. stand-alone ERD Storage Class Memory workshop in July 2012 reiterated the importance of select devices A theoretical exploration of a ‘selector-less’ memory cell needs to be performed Memory element with a build-in select element (e.g. a Schottky diode) Materials/structure optimization for both memory and selector functions Materials and Devices modeling could provide an important insight Contact resistance is an important practical performance limit ERM/ERD contact resistance e-workshop being planned

Storage Class Memory Workshop

SCM Workshop Outcome Over 50 participants Workshop presentations will be put on ITRS website Workshop results will be summarized in a report Several take-away messages A comprehensive multilevel energy analysis of different memories is needed A follow-up ERD study is planned Flexible interfaces (device-independent) A new topic for emerging architecture 'Generic' memory specs may need some discussion and rationalization Some memory devices are unlikely candidates (e.g., FRAM, Macromolecular memory)

ERD Logic Workshop 9:00 Overall workshop goals and objectives Victor Zhirnov / NCSU & SRC – USA   Session I: Circuit Requirements & Expectations for Emerging Research Devices 9:15 Digital Circuits David Frank / IBM - USA 9:45 Analog/Mixed Signal/ RF Circuits David Robertson / Analog Devices – USA 10:15 Programmable nanowire circuits for nanoprocessors Shamik Das / MITRE – USA 10:45 Break Session II: Emerging Research Devices for Nanocircuits 11:00 Tunnel FET Marc Heyns / IMEC – Belgium 11:30 CNT FET Subhasish Mitra / Stanford – USA 12:00 Graphene transistors Frank Schwierz / TU Ilmenau – Germany 12:30 – 14:00 Lunch 14:00 NEMS Devices Adrian Ionescu / EPF Lausanne – Switzerland 14:30 Atomic switch and memristor Dmitri Strukov / UC Santa Barbara – USA 15:00 MOTT FET Akihito Sawa / AIST – USA 15:30 15:45 Spin FET Viktor Sverdlov / TU Wien – Austria 16:15 Nanomagetic and all spin logic Wolfgang Porod / U Notre Dame – USA 16:45 Spin wave devices Alexander Khitun / UCLA – USA 17:15 17:30 Summary and wrap up Jim Hutchby/ SRC- USA 18:00 Adjourn

Red: devices covered in the Logic Workshop ERD Logic Devices State variable Red: devices covered in the Logic Workshop Spin wave logic Nanomagnet logic BiSFET STT logic All spin logic Charge Non-charge SpinFET Planar Si FET IMOS NEMS III-V CNT FET Atomic switch TFET GNR FET FinFET Mott FET Neg-Cg FET Mechanism Conventional Novel

Messages from the Logic Workshop (1) Logic is only a small portion of energy consumption and chip area Massive parallelism may or may not work Cost = manufacturing cost + usage cost (energy per operation) The insertion of emerging devices will be at 3D structures (e.g., FinFET, nanowire, etc.). Is surface-type device relevant? Design solutions for device problems, e.g., imperfection-immune VLSI CNT circuits Design-device-material interactions

Messages from the Logic Workshop (2) Evaluate tradeoffs in emerging devices, e.g., mobility-bandgap constraints of graphene devices How to utilize unique characteristics of emerging devices, e.g., nonvolatility, multiple states, re-programmability, etc. How to utilize unique emerging material properties, e.g., graphene/2D-materials heterostructures? How does integration impact material properties, e.g., topological insulators? Appropriate figure-of-merits to evaluate beyond-CMOS devices

Emerging Architecture Workshop Dec. 8, 2012 (Saturday), Hilton San Francisco Union Square, 333 O’Farrell Street, Room Franciscan A

Key Messages Emerging Research Memory: Emerging Research Logic: Remove Nanomechanical Memory from ERD technology table Recommend close tracking of RRAM by PIDS Workshops on Memory Select Devices and Storage Class Memory completed Quantitative data for roadmapping Implement multilevel energy analysis for different memory technologies Emerging Research Logic: Emerging logic device workshop completed: device maturity evaluation Recommend close tracking of p-III-V, n-Ge, nanowire FET, TFET by PIDS Add emerging interconnect discussions in ERD Together with RFAMS, mapping ERD devices for analog/RF applications More-than-Moore Section: New entry will be added: on-chip energy harvesting devices Develop appropriate figure-of-merits for emerging devices in MtM applications Emerging Architectures: Plan workshop on emerging research architectures (Dec. 8, San Francisco, CA) Add emerging memory interface for Storage Class Memory

Backup slides

One Diode – One Resistor (1D1R) Memory Cell H-S. P. Wong – Stanford U.

Memory Hierarchy – Future Memory Challenge SCM NVM cost/gigabyte ~ $1 Source: Al Fazio (Intel)

ERD Memory Candidates 3 nm Pt TiO2 TiO2-x oxidized reduced

Potential of Memory Candidates for SCM Applications   Prototypical (Table ERD3) Emerging (Table ERD5) Parameter FeRAM STT-MRAM PCRAM Emerging ferroelectric memory Nanomechanical memory Redox memory Mott Memory Macromolecular memory Molecular Memory Scalability MLC 3D integration Fabrication cost Endurance ? ? ? ? ? ? ?