Rawad N. Al-Haddad, Carthik A. Sharma, Ronald F. DeMara University of Central Florida Performance Evaluation of Two Allocation Schemes for Combinatorial.

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Presentation transcript:

Rawad N. Al-Haddad, Carthik A. Sharma, Ronald F. DeMara University of Central Florida Performance Evaluation of Two Allocation Schemes for Combinatorial Group Testing Fault Isolation

Agenda Overview of Group Testing AlgorithmsOverview of Group Testing Algorithms Overview of Fault Handling TechniquesOverview of Fault Handling Techniques Multi-stage Adaptive Group TestingMulti-stage Adaptive Group Testing Equal Share Allocation SchemeEqual Share Allocation Scheme Interleaved Allocation SchemeInterleaved Allocation Scheme Performance Comparison of Allocation StrategiesPerformance Comparison of Allocation Strategies

Group Testing Algorithms Origin – World War II Blood testingOrigin – World War II Blood testing Problem: Test samples from millions of new recruits Problem: Test samples from millions of new recruits Solution: Test blocks of sample before testing individual samples Solution: Test blocks of sample before testing individual samples Problem DefinitionProblem Definition  Identify subset Q of defectives from set P Minimize number of tests Minimize number of tests Test v-subsets of P Test v-subsets of P Form suitable blocks Form suitable blocks

Device Failure Duration: Target: Detection: Isolation: Diagnosis: Recovery: Transient: SEU Permanent: SEL, Oxide Breakdown, Electron Migration, LPD Repetitive Readback Device Configuration Approach: TMR BIST Processing Datapath Device Configuration Processing Datapath Bitwise Comparison Invert Bit Value Ignore Discrepancy Majority Vote STARS Supplementary Testbench Cartesian Intersection Worst-case Clock Period Dilation Replicate in Spare Resource Characteristics Methods CED Duplex Output Comparison Fast Run-time Location Select Spare Resource Duplex Output Comparison unnecessary Repetitive Intersections Evolutionary Algorithm using Intrinsic Fitness Evaluation Fault-Handling Techniques Dueling CGT-Based

Isolation Problem Outline Objectives  Locate faulty logic and/or interconnect resource: a single stuck- at fault model is assumed  Online Fault Isolation: device not entirely removed from service Two Schemes:  Equal Share:  Suspect resources are divided into equal subsets, each subset is assigned to one individual in the population,  Each suspect resource is guaranteed to be covered by at least one individual  Interleaved:  Suspect subsets are shared among individuals,  Coverage Factor (CF) determines the minimum number of individuals (  1) which utilize each resource in the suspect pool

Equal Share Allocation Allocation Strategy  Suspect pool of N LUTs  Population of R individuals  Each individual gets M suspect resources, where M = N/R.  Maximal possible gain if the fault is articulated by the test vectors is a factor of R (from N suspect resources to M)  Minimal possible testing phase gain: No gain at all if fault is not articulated

Experiments Experimental SetupExperimental Setup  DES-56 encryption circuit  Xilinx ISE design tools to place and route the design  Virtex II Pro FPGA device  Fault Injection and Analysis Toolkit (FIAT) Application Programmer Interfaces (APIs) to interact with the Xilinx ISE tools to inject and evaluate faults Application Programmer Interfaces (APIs) to interact with the Xilinx ISE tools to inject and evaluate faults Editing the design file rather than the configuration bitstreamsto introduce stuck-at-faults Editing the design file rather than the configuration bitstreams to introduce stuck-at-faults Editing User Constraint Files (UCF) to control resource usage Editing User Constraint Files (UCF) to control resource usage

Equal Share Results Total number of runs for each group count Number of test vectors required in each run Results of three CGT experiments with different population size Population Isolation resultsNumber of groups Required Test vectors Discrepancies SuccessFail3456MeanSD

Interleaved Allocation Allocation Scheme  Each LUT in the suspect pool is utilized by more than one individual in the population  Implies “interleaving” of individuals over each LUT.  Interleaving degree decided by Coverage Factor.  Coverage factor (CF): Number of individuals utilizing each resource in the suspects pool  Example: CF = 2 means that each suspected LUT is covered by two different individuals.

Interleaved Allocation Scheme  N LUTs divided into M subgroups where M = N/R  Each individual utilizes 2  M LUTs  Discrepancy will reduce the number of suspects to 2M rather than M  However, (100/CF)% less chance of unarticulated faults. Interleaved Allocation scheme with CF = 2

Two-Pass Algorithm Pass one:Pass one:  Reduce suspect list from N to CF  N/R, where CF is the coverage factor  Isolation granularity gain is reduced when CF is increased.  Terminated once the first discrepant output is observed. Pass TwoPass Two  Reduce suspect list from CF  N/R to N/R (same gain as Equal Share)  New data structure is introduced to expedite the process.  Called Interleaved Individuals Set (IIS)

Interleaved Individuals Set Purpose:Purpose:  Keep track of the interleaved individuals in a specific CGT configuration Example:Example: In pass two, individuals interleaving with the one which articulated the fault in pass one will be tested. In pass two, individuals interleaving with the one which articulated the fault in pass one will be tested.

Conclusion Equal Share:Equal Share:  Best Case: Suspect List reduced from N to N/R  Worst Case: Zero gain (unarticulated fault)  One pass only InterleavedInterleaved  Best Case: Suspect List reduced from N to N/R  Performed in two passes (N  CF  N/R  N/R)  IIS minimizes overhead in Pass two  Worst Case: Zero gain also.  BUT, less chance to occur than Equal share scheme (because of interleaving)

References  Sharma, C. A. and R. F. DeMara (2006), “A Combinatorial Group Testing Method for FPGA Fault Location,” in Proceedings of the International Conference on Advances in Computer Science and Technology (ACST 2006), Puerto Vallarta, Mexico, 2006  Du D and Hwang, F. K (2000), "Combinatorial Group Testing and its Applications," Series on Applied Mathematics volume 12, World Scientific.  Sharma, C. A. (2007), "FPGA Fault Injection and Analysis Toolkit (FIAT)."