1 Process-Variation Tolerant Design Techniques for Multiphase Clock Generation Manohar Nagaraju +, Wei Wu*, Cameron Charles # + University of Washington, Seattle, WA, USA # University of Utah, Salt Lake City, UT, USA *Northwestern Polytechnic University, Xi’an, China

Outline Background on clock and data recovery (CDR) and motivation Circuit level and system level optimization Measurement results Conclusion 2

Motivation Increasing I/O bandwidth complicates CDR circuit design, particularly the VCO Solution: over-sample the incoming data 3

Motivation Use a Delay-Locked Loop (DLL) to recover data at N*clock frequency 4

Motivation Problems in multiphase clock generation  Mismatch in delay among delay blocks  Overall frequency controlled by loop but phase relationships uncontrolled 5 Input Data Ideal Sampling Non-Ideal Sampling

Delay Distribution of inverter pair V t mismatch of 100mV Motivation Sources of mismatch  Mismatch in Vt  Mismatch in W/L 6

Motivation Sources of mismatch  Mismatch in Vt  Mismatch in W/L  Mismatch in load 7 Delay of stage 1: 686.3ps Delay of stage 2: 695.5ps Delay of stage 3: 695.5ps Delay of stage 4: 654.5ps

Solution Propose circuit-level design methodology to reduce mismatch Introduce extra control on the individual phases – digital calibration 8

Circuit-level optimization A transistor sizing scheme to reduce mismatch Expression for variable of interest (here delay) as a function of process parameter (here V t ) Differentiate w.r.t process parameter Design circuit to ensure the resulting expression is small 9

Circuit-level optimization 10 Ex: A CMOS inverter Fall time: Following procedure, length should be increased

Circuit-level optimization 11 Schematic of a single delay cell Increase W/L Reduce W/L Increase W/L

Circuit optimization results Monte-Carlo simulation 12 a)Optimized co-efficient of variation = 3.05% b) Un-optimized co-efficient of variation = 6.73%

Limitation VCDL gain becomes non-linear 13

Limitation VCDL gain becomes non-linear Lock range of DLL reduces 0.5 T ref clk < T VCDL, min < T ref clk T ref clk < T VCDL max < 1.5 * T ref clk Process complicated with the number of variables increasing Delay still varies from ps (5.57˚) – quite large for multiphase clocking scheme 14

Phase control by digital calibration Based on equation f ring_osc = (1/2NT d ) 15

Calibration of the VCDL Difference between ring oscillator frequencies indicates difference in delays To change delay of delay block  Change V t - requires DAC  Change current which is the parameter of interest – by changing widths dynamically 16

Calibration of the VCDL 17 Modify delay cell Resolution = 9.8ps Delay variation -140ps

Die photo AMI 0.6um CMOS process um X 900um 18

Measurement results Lock range – MHz Power: 15.4mA mA (calibration) Time required for calibration 8.29us. 19

Measurement results 20 Delay Block Ideal Delay (ns) Delay value (ns) Error (ns) Delay Phases Ideal Sampling time (ns) Actual Sampling time (ns) Error in Sampling time (ns) Φ1 –Φ Φ1 –Φ Φ1 –Φ Delay Block Ideal Delay (ns) Delay value (ns) Error (ns) Delay Phases Ideal Sampling time (ns) Actual Sampling time (ns) Error in Sampling time (ns) Φ1 –Φ Φ1 –Φ Φ1 –Φ Delay values of the four delay blocks before and after calibration at 227MHz 3.28˚ 1.09˚ 0.4˚

Performance summary 21 This workJSSC May ‘06 TCAS II July ‘08 Process0.6um0.18um0.13um Frequency range MHz0.7-2GHzN/A Calibration methodDigital Analog Phase error before calibration 227MHz 2GHz N/A Phase error after calibration Area of calibration circuit 1.17mm mm 2 N/A Power77mW81mW16.4mW

22 Proposed a new methodology to design process-invariant circuits Proposed a digital calibration scheme to reduce mismatches in delay Maximum phase offset among delay blocks was reduced to 1.09° Summary

Thank You 23