Marseille 30 January 2013 David Calvo IFIC (CSIC – Universidad de Valencia) CLB: Current status and development on CLBv2 in Valencia

TDC: DESIGN DESERIALIZER RECOVERY UNIT FIFO Output 48 bits ( Resolution: 1ns ) 8 bits KC bits Time StampHeader 8 bits Pulse width LVDS Input Signal

TDC: 31 CHANNELS LVDS Input Signal Output (48 bits) KC705 3 MULTIPLEXER Ch.1 Ch.2 Ch.31 SIGNAL DISTRIBUTION Enable Interface Ch.1 Ch.31 PC

TDC: TEST ML605 LVDS Input Signal Output (48 bits) KC705 4 Well-known pattern MULTIPLEXER Ch.1 Ch.2 Ch.31 SIGNAL DISTRIBUTION Enable Interface Ch.1 Ch.31 PC

TDC: PATTERNS TO TEST Jitter = 0.3 ns 5 CHANNEL 1 CHANNEL 2

TDC: PATTERN TO TEST 6 Patterns replicated 250 times 1000 pulses x channel CHANNEL 1 CHANNEL 2

TDC: RESULT 7 Pulse width ns counts CHANNEL 1 ns counts CHANNEL 2

TDC: RESULT 8 Time between pulses ns counts CHANNEL 1 ns counts CHANNEL 2

I2C1 LM32 DEVELOPMENTS IN VALENCIA LM32 SOC with several wishbone slaves (32 bits bus): o BRAM o UART o TIMER o I2C0 Nanobeacon o I2C1 Temperature and Humidity sensor (DIGIPICCO) o GPIO 2 nd CPU LM32 B RAM I2C0UART Data Wishbone shared bus (32 bits) Nano Beacon GPIO Debug LEDs TIMER RS-232 HYPERTERMINAL Xilinx Spartan-6 Temp and Humidity Sensor

LM32 DEVELOPMENTS IN VALENCIA Rx_mac2buf I2C Fifo 31 TDCs TDC0 Management & Control Data Control Wishbone bus RxPacket Buffer 64KB IP/UDP Packet Buffer Stream Selector (IPMUX) Rx_buf2data RxPort 1 RxPort 2 RxPort_m Management & Config. Tx_pkt2mac Tx_data2buf TxPort 1 TxPort 2 TxPort_m Flags Rx Stream Select TxPacket Buffer 32KB Flags Tx Stream Select 31 PMTs UTC time & Clock (PPS, 125 MHz) Pause Frame ADC Management & Control Hydrophone Fifo TDC 30 Fifo Nano Beacon GPIO Debug LEDs I2C Debug RS232 Temp Compass Tilt Point to Point interconnection Xilinx Kintex-7 Start Time Slice UTC & Offset counter since Time Slice Start MEM S 2 nd CPU LM32 M M WB Crossbar (1x7) WB Crossbar (3x2) S M S M M S S M M M SS S UART S M M S S M M State Machine SPI S M Flash

NEXT STEPS IN VALENCIA (I) Rx_mac2buf I2C Fifo 31 TDCs TDC0 Management & Control Data Control Wishbone bus RxPacket Buffer 64KB IP/UDP Packet Buffer Stream Selector (IPMUX) Rx_buf2data RxPort 1 RxPort 2 RxPort_m Management & Config. Tx_pkt2mac Tx_data2buf TxPort 1 TxPort 2 TxPort_m Flags Rx Stream Select TxPacket Buffer 32KB Flags Tx Stream Select 31 PMTs UTC time & Clock (PPS, 125 MHz) Pause Frame ADC Management & Control Hydrophone Fifo TDC 30 Fifo Nano Beacon GPIO Debug LEDs I2C Debug RS232 Temp Compass Tilt Point to Point interconnection Xilinx Kintex-7 Start Time Slice UTC & Offset counter since Time Slice Start MEM S 2 nd CPU LM32 M M WB Crossbar (1x7) WB Crossbar (3x2) S M S M M S S M M M SS S UART S M M S S M M State Machine SPI S M Flash

NEXT STEPS IN VALENCIA (II) Rx_mac2buf I2C Fifo 31 TDCs TDC0 Management & Control Data Control Wishbone bus RxPacket Buffer 64KB IP/UDP Packet Buffer Stream Selector (IPMUX) Rx_buf2data RxPort 1 RxPort 2 RxPort_m Management & Config. Tx_pkt2mac Tx_data2buf TxPort 1 TxPort 2 TxPort_m Flags Rx Stream Select TxPacket Buffer 32KB Flags Tx Stream Select 31 PMTs UTC time & Clock (PPS, 125 MHz) Pause Frame ADC Management & Control Hydrophone Fifo TDC 30 Fifo Nano Beacon GPIO Debug LEDs I2C Debug RS232 Temp Compass Tilt Point to Point interconnection Xilinx Kintex-7 Start Time Slice UTC & Offset counter since Time Slice Start MEM S 2 nd CPU LM32 M M WB Crossbar (1x7) WB Crossbar (3x2) S M S M M S S M M M SS S UART S M M S S M M State Machine SPI S M Flash

NEXT STEPS IN VALENCIA (III) Rx_mac2buf I2C Fifo 31 TDCs TDC0 Management & Control Data Control Wishbone bus RxPacket Buffer 64KB IP/UDP Packet Buffer Stream Selector (IPMUX) Rx_buf2data RxPort 1 RxPort 2 RxPort_m Management & Config. Tx_pkt2mac Tx_data2buf TxPort 1 TxPort 2 TxPort_m Flags Rx Stream Select TxPacket Buffer 32KB Flags Tx Stream Select 31 PMTs UTC time & Clock (PPS, 125 MHz) Pause Frame ADC Management & Control Hydrophone Fifo TDC 30 Fifo Nano Beacon GPIO Debug LEDs I2C Debug RS232 Temp Compass Tilt Point to Point interconnection Xilinx Kintex-7 Start Time Slice UTC & Offset counter since Time Slice Start MEM S 2 nd CPU LM32 M M WB Crossbar (1x7) WB Crossbar (3x2) S M S M M S S M M M SS S UART S M M S S M M State Machine SPI S M Flash

NEXT STEEPS IN VALENCIA (IV) Implement reconfigurability: A.- To use the multiboot capabilities of the KINTEX B.- To be able to write on the SPI FLASH with the LM32 2 nd CPU LM32 SPI Data Wishbone shared bus (32 bits) Multiboot image – upgraded image (read /write) Golden Image (read only) Xilinx Kintex KC705 SPI QFLASH MEMORY

THANKS FOR YOUR ATTENTION!

LM32 developments in Valencia Rx_mac2buf I2C Fifo 31 TDCs TDC0 Management & Control Data Control Wishbone bus RxPacket Buffer 64KB IP/UDP Packet Buffer Stream Selector (IPMUX) Rx_buf2data RxPort 1 RxPort 2 RxPort_m Management & Config. Tx_pkt2mac Tx_data2buf TxPort 1 TxPort 2 TxPort_m Flags Rx Stream Select TxPacket Buffer 32KB Flags Tx Stream Select 31 PMTs UTC time & Clock (PPS, 125 MHz) Pause Frame ADC Management & Control Hydrophone Fifo TDC 30 Fifo Nano Beacon GPIO Debug LEDs I2C Debug RS232 Temp Compass Tilt Point to Point interconnection Xilinx Kintex-7 Start Time Slice UTC & Offset counter since Time Slice Start MEM S 2 nd CPU LM32 M M WB Crossbar (1x7) WB Crossbar (3x2) S M S M M S S M M M SS S UART S M M S S M M State Machine SPI S M Flash