Crosstalk Analysis in UDSM technologies

Slides:



Advertisements
Similar presentations
EE 201A Modeling and Optimization for VLSI LayoutJeff Wong and Dan Vasquez EE 201A Noise Modeling Jeff Wong and Dan Vasquez Electrical Engineering Department.
Advertisements

EE141 © Digital Integrated Circuits 2nd Wires 1 The Wires Dr. Shiyan Hu Office: EERC 731 Adapted and modified from Digital Integrated Circuits: A Design.
UCLA Modeling and Optimization for VLSI Layout Professor Lei He
By Jonathan Coup.  Crosstalk is the transfer of energy between adjacent conductors due to either capacitive or inductive coupling.  In order for crosstalk.
EE 587 SoC Design & Test Partha Pande School of EECS Washington State University
1 On Convergence of Switching Windows Computation in Presence of Crosstalk Noise Pinhong Chen* +, Yuji Kukimoto +, Chin-Chi Teng +, Kurt Keutzer* *Dept.
Noise Model for Multiple Segmented Coupled RC Interconnects Andrew B. Kahng, Sudhakar Muddu †, Niranjan A. Pol ‡ and Devendra Vidhani* UCSD CSE and ECE.
Fall 06, Sep 19, 21 ELEC / Lecture 6 1 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic.
EE466: VLSI Design Lecture 11: Wires
EE 447 VLSI Design Lecture 5: Wires. EE 447VLSI Design 6: Wires2 Outline Introduction Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering.
IC Interconnect Modeling Dr. Paul Van Halen PROBLEM  Resistive, capacitive and inductive effects in circuit interconnect.
EELE 461/561 – Digital System Design Module #5 Page 1 EELE 461/561 – Digital System Design Module #5 – Crosstalk Topics 1.Near-End and Far-End Crosstalk.
EE4271 VLSI Design Interconnect Optimizations Buffer Insertion.
04/11/02EECS 3121 Lecture 26: Interconnect Modeling, continued EECS 312 Reading: 8.2.2, (text) HW 8 is due now!
Transition Aware Global Signaling (TAGS)  Proposed as an alternative to standard inverter receivers  Enables a 15mm unbuffered line with a 800MHz global.
S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 15: Interconnects & Wire Engineering Prof. Sherief Reda Division of Engineering,
The Wire Scaling has seen wire delays become a major concern whereas in previous technology nodes they were not even a secondary design issue. Wire parasitic.
EELE 461/561 – Digital System Design Module #6 Page 1 EELE 461/561 – Digital System Design Module #6 – Differential Signaling Topics 1.Differential and.
Crosstalk Overview and Modes.
EE141 © Digital Integrated Circuits 2nd Wires 1 Digital Integrated Circuits A Design Perspective The Wire Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.
04/09/02EECS 3121 Lecture 25: Interconnect Modeling EECS 312 Reading: 8.3 (text), 4.3.2, (2 nd edition)
Lecture 24: Interconnect parasitics
Ryan Kastner ASIC/SOC, September Coupling Aware Routing Ryan Kastner, Elaheh Bozorgzadeh and Majid Sarrafzadeh Department of Electrical and Computer.
Noise and Delay Uncertainty Studies for Coupled RC Interconnects Andrew B. Kahng, Sudhakar Muddu † and Devendra Vidhani ‡ UCLA Computer Science Department,
1 Encoding-based Minimization of Inductive Cross-talk for Off-Chip Data Transmission Brock J. LaMeres Agilent Technologies, Inc. Sunil P. Khatri Dept.
Link A/D converters and Microcontrollers using Long Transmission Lines John WU Precision Analog - Data Converter Applications Engineer
EE 587 SoC Design & Test Partha Pande School of EECS Washington State University
ECE 424 – Introduction to VLSI Design
EE466: VLSI Design Power Dissipation. Outline Motivation to estimate power dissipation Sources of power dissipation Dynamic power dissipation Static power.
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line.
EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Chapter 7 Programmable.
Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Topics n Interconnect design. n Crosstalk. n Power optimization.
TDS8000 and TDR Considerations to Help Solve Signal Integrity Issues.
Chapter 07 Electronic Analysis of CMOS Logic Gates
INTRODUCTION Interconnection wiring is gaining a significant importance in speed of modern VLSI circuits. Since the wiring may cover up to eighty percent.
EE141 © Digital Integrated Circuits 2nd Wires 1 Digital Integrated Circuits A Design Perspective The Interconnect Jan M. Rabaey Anantha Chandrakasan Borivoje.
EE415 VLSI Design 1 The Wire [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]
EE141 © Digital Integrated Circuits 2nd Wires 1 Digital Integrated Circuits A Design Perspective The Wire Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.
Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Topics n Interconnect design. n Crosstalk. n Power optimization.
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 30: November 19, 2010 Crosstalk.
11/22/2004EE 42 fall 2004 lecture 351 Lecture #35: data transfer Last lecture: –Communications synchronous / asynchronous –Buses This lecture –Transmission.
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 33: November 20, 2013 Crosstalk.
Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Topics n Wire delay. n Buffer insertion. n Crosstalk. n Inductive interconnect. n Switch logic.
© Digital Integrated Circuits 2nd Inverter Digital Integrated Circuits A Design Perspective The Inverter Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.
By Nasir Mahmood.  The NoC solution brings a networking method to on-chip communication.
Chapter 4: Secs ; Chapter 5: pp
Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Topics n Wire delay. n Buffer insertion. n Crosstalk. n Inductive interconnect.
Inductance Screening and Inductance Matrix Sparsification 1.
Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits Yehea I. Ismail and Eby G. Friedman, Fellow, IEEE.
CSE477 L27 System Interconnect.1Irwin&Vijay, PSU, 2003 CSE477 VLSI Digital Circuits Fall 2003 Lecture 27: System Level Interconnect Mary Jane Irwin (
CARBON NANOTUBES (A SOLUTION FOR IC INTERCONNECT) By G. Abhilash 10H61D5720.
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 30: November 21, 2012 Crosstalk.
CROSSTALK, Copyright F. Canavero, R. Fantino Licensed to HDT - High Design Technology.
High Speed Properties of Digital Gates, Copyright F. Canavero, R. Fantino Licensed to HDT - High Design Technology
TERMINATIONS Copyright F. Canavero, R. Fantino Licensed to HDT - High Design Technology.
Worst Case Crosstalk Noise for Nonswitching Victims in High-Speed Buses Jun Chen and Lei He.
Power-Optimal Pipelining in Deep Submicron Technology
Crosstalk If both a wire and its neighbor are switching at the same time, the direction of the switching affects the amount of charge to be delivered and.
Topics Driving long wires..
Jason Cong, David Zhigang Pan & Prasanna V. Srinivas
SIDDAGANGA INSTITUTE OF TECHNOLOGY
SIDDAGANGA INSTITUTE OF TECHNOLOGY
Day 33: November 19, 2014 Crosstalk
Day 31: November 23, 2011 Crosstalk
ELEC 7770 Advanced VLSI Design Spring 2010 Interconnects and Crosstalk
Circuit Design Techniques for Low Power DSPs
Inductance Screening and Inductance Matrix Sparsification
Jason Cong, David Zhigang Pan & Prasanna V. Srinivas
Presentation transcript:

Crosstalk Analysis in UDSM technologies Based on the work presented in “Crosstalk Noise Analysis in Ultra Deep Submicrometer Technologies” by : , Kannan S. Tharmalingam and Magdy A.bayoumi Proceedings of the IEEE Computer Society Annual Symposium on VLSI. By :Arashk Noroozpour Professor : Dr. S.M. Fakhraie

Interconnect Delay and Noise The interconnect delay and noise have become the dominant factors in determining circuit performance. [1] Crosstalk noise, which is known as coupling noise, imposes three side effects on digital design: It can affect timing, causing a delay failure. It can increase the power consumption due to glitches. It can cause functional failure. [1] Coupling capacitance between neighboring nets is a dominant component in today’s DSM design. Noise from inductive coupling can also present problems for VLSI wires. [2] Scaling could affect both capacitive and inductive noises. [2]

Impact of Noise on Circuit Performance and Interconnect/Driver parameters Place of crosscoupling Signal direction between two parallel wires The Operating Frequency Spacing , wire length , wire width, resistances Coupling length Input rise-time Driver strength Peak Noise Amplitude (for victim) Aggressor Delay Noise Pulse Width

Transmission Line Model Using three transmission lines allows us to vary L1, L2, L3 separately, and to be able to accurately notice the effects of each of the wire length and the cross-coupling length. The figure on top shows the transmission line model, and the figure below shows three transmission lines with 2 conductors. [1]

Simulations: Victim Amplitude vs. spacing The noise relatively decreases faster for a small Ra. [1] The aggressor and victim widths have approximately no effect on the noise amplitude. [1] The effect of wire sizing diminishes if the coupling location is close to victim driver. But it is very effective when coupling location is close to victim receiver. [1] Spacing could be so effective for long coupling lengths.

Noise and Aggressor Delay For the effect of sizing on the aggressor delay, Table 1 shows results. The effect of aggressor and victim wire lengths with a constant coupling length between them, shown in the right-hand-side figure. The peak noise decreases as the aggressor length increases as long as the coupling length is kept constant. Victim length has no effect on the aggressor wire delay.

The Impact of the Coupling Length The figure on top shows the increase of the victim peak amplitude with the increase of the coupling length. This is of course due to the coupling capacitance. Aggressor delay is also affected by coupling length, especially for larger input rise-times. Another important parameter that affects the noise especially in high-speed circuits is the input rise-time.

Noise Pulse Width Noise pulse width is affected with spacing. Now we have three metrics for the noise: peak noise amplitude noise pulse width peak noise occurring time Some noise-avoidance techniques like increasing the spacing between two adjacent lines , and driver sizing or wire sizing seem to be reasonable.

Capacitive and Inductive Coupling Capacitive coupling is a large problem for weakly driven nodes. [2] Inductive coupling pushes the victim in the opposite direction from the capacitive coupling: a rising aggressor capacitively couples the victim up, but inductively couples the victim down.[2] While capacitive coupling is mostly the “nearest neighbor” phenomenon, inductive coupling has a much larger range. [2] Inductive noise becomes a problem only when a large number of wires switch at the same time in bus-like situations. [2]

Scaling effects on wire metrics Noise coupling both capacitive and inductive, should be mostly unchanged under scaling as long as the wires scale in length. For wires that do not scale in length, inductive noise can grow relative to the power supply, but more likely, these wires will be repeated. Repeaters break up the current return paths effectively, making each repeated segment independent from the rest, and preventing inductive noise from growing over technologies. Wires: Wires that scale in length: the wire delay scales with technology, showing constant resistance and falling capacitance. Wires that do not scale in length: show an increasing disparity with gate delays. Designers rarely use global wires without repeaters. The increase in noise for long wires is another reason for using repeaters.

Conclusions Interconnect/Driver parameters can affect crosstalk noise metrics. Noise metrics such as peak noise amplitude, aggressor delay and noise pulse width are the most important of all. Both capacitive and inductive coupling, can present noise and thus threat functionality. Inductive coupling pushes the victim in the opposite direction from the capacitive coupling Wire scaling could have different effects on noise performance due to capacitive and inductive coupling. Wires scale diversely due to technology scaling, local wires scale in length, while global wires do not.

References 1. Crosstalk Noise Analysis In Ultra Deep Submicrometer Technologies by: Mohamed A.Elgamel, Kannan S. Tharmalingam and Magdy A. Bayoumi proceedings of the IEEE Computer Society Annual Symposium on VLSI 2.The Future of Wires by: RON HO, MEMBER, IEEE, KENETH W.MAI, STUDENT MEMBER, IEEE, and MARK A. HOROWITZ, FELLOW IEEE proceedings of the IEEE 3.Digital Integrated Circuits: A Design Perspective by: JAN M. RABAEY , ANATHA CHANDRAKASAN, BORIVOJE NIKOLIC