Advanced Digital Circuits ECET 146 Week 7 Professor Iskandar Hack ET 221B,

This Week’s Goals Adding a Time Delay to a Simple Finite State Machine Designing a Simple Control System using VHDL with a FSM

Time Delay Function This is a separate project that allows the designer to specify a particular amount of time (in clock cycles) that the main project will remain in a particular state This project has as it’s inputs clk, reset, nsec (the number of clock cycles to remain in that state) and start The only output of this project is te (time expired)

SubDesign for timedelay Can be scaled up or Down depending on Number clock cycles Needed NOTE – Use [3..0] instead

Variable Section for timedelay Note: we are specifying that we want to keep track of Count using d-ff’s In this case we’re using 5 dff’s for count (NOTE – the version I uploaded is count[3..0] We have 3 states, one waiting to start counting, one to start the counter, and another where we are decrementing count until it reaches zero

Set up for the FF’s used in timedelay Sets up the clk and reset signal for the state machine ff’s Sets up the clk and reset signal for the count d-ff’s (note that a dff has a input clrn not that we use !reset (the ! Symbol inverts the reset signal

The Case Statement This is similar to programming languages in that you can look a particular signal and determine what you want the logic do based on the contents of that signal The syntax is shown on the next slide for the logic in the timedelay function This case statement is the heart of timedelay

Case Statement in timedelay CASE ss IS WHEN idle => te = vcc; if start then ss = startstate; else ss = idle; end if; WHEN startstate => te = gnd; count[].d = nsec[]; if start then ss = startstate; else ss = counting; end if; WHEN counting => if start then ss = startstate; else count[].d = count[].q - 1; if count[].q == b"00000" then ss = idle; te = vcc; else ss = counting; te = gnd; end if; END CASE; Waiting for start to go High before counting Start has gone high, so save the number of clock cycles to delay on the count dff’s and wait for start to go low In case we want to start counting again Subtract 1 from the output (q) of the ff’s and place them on the inputs (d) of the ff’s Check if we’re done, if so take te high otherwise keep counting

Complete TimeDelay Function (cut and paste) SUBDESIGN timedelay ( clk : INPUT; reset : INPUT; start : INPUT; nsec[3..0] : INPUT; te : OUTPUT; ) VARIABLE ss: MACHINE WITH STATES (idle, startstate, counting ); count[3..0] :dff; BEGIN count[].clk = clk; count[].clrn = !reset; ss.clk = clk; ss.reset = reset; CASE ss IS WHEN idle => te = vcc; if start then ss = startstate; else ss = idle; end if; WHEN startstate => te = gnd; count[].d = nsec[]; if start then ss = startstate; else ss = counting; end if; WHEN counting => if start then ss = startstate; else count[].d = count[].q - 1; if count[].q == b"0000" then ss = idle; te = vcc; else ss = counting; te = gnd; end if; END CASE; END;

Save, compile and made default symbol for timedelay Go through the normal steps after copying and pasting the function timedelay into the text editor Open timedelay.tdf Make default symbol for timedelay

Example Project that uses timedelay In this project we’re going to go from state s0 to s1 after 5 clock cycles, to s2 after 8 clock cycles and back to s0 after 3 clock cycles. We’re going to have the following outputs: Y1 – high during s0 Y2 – high during s1 and s2 Y3 – high only during s2

Some points to remember We have to as outputs from our new project the signals for timedelay (start and nsec) We have to have an input for te We have to subtract from the variable nsec one clock cycle for the startstate clock cycle We have to have a unique state to “START” the timedelay function We have to have a ‘loop-back’ to the same state until te goes high

Bubble Graph for Simple w/timedelay Design

Table to show State Transistions Current StateTE (the only input that has an effect on table transitions Next State S0X (don’t care)S0a 0 1S1 X (don’t care)S1a 0 1S2 X (don’t care)S2a 0 1S0

Table to show Outputs Current StateNsec[]STARTY1Y2Y3 S04VCC GND S0a4GNDVCCGND S18VCCGNDVCCGND S1a8GND VCCGND S22VCCGNDVCC S2a2GND VCC

Entity and Start of Architecture

Begin and Start the Process

State Transition

Define the Output for Each State

Save and Compile Example Save as exampleweek6.tdf Compile (ignore warnings) Create Default Symbol

Start Final Design (uses both timedelay and exampleweek6 Open Block/Schematic Editor and add the inputs, outputs and the two symbols just designed. NOTE – ALL files must be in the same directory, don’t create separate directories for the three projects

Final Design Drawing Note must be a BUS

Save as NEW Project Name Save drawing as week6final.bdf Change Top-Level to current project Save and Compile Define Device and I/O pins

Simulation Same as before except you’ll need to change the end time to at least 4.5uS to see complete cycle Note you can see the internal state machine states along with the count – again helps with troubleshooting non-working designs

Div_Clock In order to see clock transitions we must slow down the clock from the on-board clock Clock used on DE0 is 50 MHz Need to reduce the frequency or divide down the clock to 1 Hz for real time testing

Div_clock Code LIBRARY IEEE; USE ieee.std_logic_1164.ALL; ENTITY div_clock IS PORT(clk_in:IN std_logic; clk_out:BUFFER std_logic); END div_clock; ARCHITECTURE behavior OF div_clock IS SIGNAL reg :integer RANGE 0 TO ; BEGIN PROCESS(clk_in) BEGIN if rising_edge(clk_in) then if (reg= ) then clk_out<=not(clk_out); reg <= 0; else reg<= reg + 1; end if; end process; end behavior;

Lab 6 Introduction to State Machines and Time Delay Watch the video for Week 7 before starting!!!! Design using the techniques discussed in class a Finite State Machine (FSM) that will simulate a basic stop light with the MAJOR states shown on the next slide. (You can shorten the times if desired; these times seem to last forever when trying to verify the project) Please Note that inside each state there needs to be several sub-states that perform the following. a)Place on the output of the FSM the number of seconds (minus 1) that the FSM is to remain in that state, and sets the start signal high. b)Removes the start signal (to start the timedelay component), and number of seconds c)Waits until the TE signal goes high from timedelay d)Please note that during all of these sub-states the outputs have to be set correctly, this is NOT a computer program that the outputs are set until changed – they must be specified for ALL states and sub-states (look at the example which had s0, s0a for s0) After simulation add div_clk block, assign pins, assign unused pins to tri-state, and recompile Download on board and test. Submit a Formal Lab Report using the Standard ECET format

Lab 5 Table State NameOutputsTime EWGNS - R15 EW - G EWYNS - R5 EW-Y EWRNS - R2 EW - R NSGNS-G15 EW-R NSYNS-Y5 EW-R NSRNS-R2

Hints Use Pin G21 for clock input (you must use DIV_CLOCK, otherwise all LED’s will be on) Use LED0 – LED3 for North-South lights (we’ll be using the 4 th LED on the next lab) Use LED4-LED7 for East-West lights Use a Single 8-bit output assigned to the 8-LEDs Use the following format for the LED’s Red Yellow Green (Not used) Example 0 to turn on the Red NS light and Green EW light you need to output to the LED output LED = x”82” Use an 8-Bit Integer for all LED’s

Output Pins