Modifications to the Pixel ROC Hans-Christian Kästli

Hans-Christian Kästli June 8, New Pixel Mechanics In addition: 3 disks on each side instead of 2 Add 4 th layer : 39(29?),68,109 & 160 mm beam pipe clearance 4(<2) mm 8 modules along z (1216 total) ‘ultra‘ light support structure CO 2 based cooling system  Less material  more robust (standalone) tracking  better connection to strip tracker

Hans-Christian Kästli June 8, Prototype Layer 1 prototype: 200  m carbon fiber 4mm Airex foam Stainless steel tubes: –1.5 mm OD, 50  m wall –Tube bends: 1.8mm OD, 100  m wall tested: ~100 bar & -10 o C..10 o C Factor >3 gain in material budget  4 layer system will have half of MB of old 3 layer system

Hans-Christian Kästli June 8, Constraints and Requirements Same/better performance: Higher efficiency at higher rates reduce material effects (multiple scattering, photon conversion) Have to use existing services: Cooling pipes, power cabling, fibers But we have 60% more modules data rate  faster readout (digital) Power  DC-DC converters Short commissioning time: We are in a competitive physics situation  Leave system unchange as much as possible keep ROC core untouched, it is well debuged. Keep control links as is. This leaves pixel operation similar to today

Hans-Christian Kästli June 8, ROC modifications Higher rate capability –Larger L1 latency buffers with denser layout to reduce trigger latency related data losses –Additional readout buffer stage to lower readout related data losses Change readout to digital scheme –Substantially increase readout bandwidth Lowering operational signal threshold –Lower threshold translates directly into longer lifetime of detector (less charge from sensor) Miscellanea –Operational improvements –Further optimization of current consumption

Hans-Christian Kästli June 8, Improving hit rate capability

Hans-Christian Kästli June 8, L1 Trigger Latency Buffers Number of occupied TS buffer cells Number of occupied data buffer cells # events Buffer sizes of PSI46 Simulation of buffer occupancies: physics event generators for signal and min bias events + GEANT4 full detector simulation

Hans-Christian Kästli June 8, Larger L1 latency buffers Data Buffer –layout of reduced cell size done –data losses simulated for 3.9cm radius done –simulate or extrapolate data losses for first pixel layer at r=2.9cm (12 faces) and decide on final data buffer depth. to do –calculate final ROC size.vs. data buffer depth to do Time Stamp Buffer –cell size estimatedone –data losses simulated for 3.9cm radiusdone –simulate or extrapolate data losses for first pixel layer at r=2.9cm (12 faces) and decide on final time stamp buffer depthto do –calculate final ROC size.vs. time data buffer depth to do

Hans-Christian Kästli June 8, Buffered Readout present ROCnew ROC Double columns with verified data stops  no more events accepted until r/o finished Double columns have to wait for external token  long dead time Sequential readout of 16 ROCs  high token delay DCol readout parallel in all ROCs after trigger  reduced waiting time ROC readout buffer: read/write simultaneous; data with different time stamps Easy implementation in separate buffer on ROC  keep present DCol logic External readout token

Hans-Christian Kästli June 8, Readout Buffer 64 x 24 bit static RAM with address decoder in each cell Simultaneous read and write (synchronous to clock) Two 6 bit counters for read and write pointer, IO buffer 24 bit cell size: µm x 124 µm 64 cells & control logic: 3800 µm x 124 µm (L x W) Space for = 96 cells (5640 µm) if needed (simulations for final depth needed) Status: Schematic, Layout of RAMdone Control logic with countersdone Simulation with parasitic R and C (long busses)done Insertion in ROC (insertion study done)to do

Hans-Christian Kästli June 8, Change to digital readout scheme

Hans-Christian Kästli June 8, Digital Data Format Running at 160 MHz from ROC to TBM, 320 MHz from TBM to FED Needs fast on chip ADC running at 80 MHz

Hans-Christian Kästli June 8, Digital Data Format Running at 160 MHz from ROC to TBM, 320 MHz from TBM to FED Needs fast on chip ADC running at 80 MHz

Hans-Christian Kästli June 8, Upgrade to Digital Readout

Hans-Christian Kästli June 8, Critical building blocks PLL for 160 MHz –Components designed and tested. Work very well. –Irradiation tests with 60 Co source made with ring oscillator at PSI by Indira (PIRE student) up to 40 Mrad. –Max frequency reduced by <10%. Still above 440 MHz –Will continue to irradiate Serializer running an 160 MHz. To be tested Output signal driver. Slight improvements will be made ADC running at 80 MHz (see next slide)

Hans-Christian Kästli June 8, Towards a lower signal threshold

Hans-Christian Kästli June 8, Where to set the threshold? Low threshold is beneficial because: charge sharing improves the position resolution, but means lower charge per pixel Highly irradiated detectors give lower signal charges due to trapping and partial depletion Why can’t we just set the threshold to arbitrary low values then? Naïve answer: because of noise –We want the pixel to trigger only on real physical pulses –Noise leads to random hits. Too many of them will make the ROC inefficient or completely dead In reality: noise gives only lower bound on threshold, but practical (stable) threshold is way above that (  X-talk)

Hans-Christian Kästli June 8, From Jose’s talk

Hans-Christian Kästli June 8, From Jose’s talk All electronic circuits have noise on top of their signals zoom in

Hans-Christian Kästli June 8, From Jose’s talk All electronic circuits have noise on top of their signals If noise amplitude has gaussian distribution, threshold scan gives “S-curve” instead of step function Width = noise. Typical 150 e- zoom in

Hans-Christian Kästli June 8, ROC internal X-talk to analog inputs Lowest achievable threshold in ROC tuning (~3000 e-) far above amplifier noise (~150e-) Similar observation for all 3 LHC experiments with pixels Reason must be chip internal x-talk, since the chip is essentially mixed signal (i.e. analog and digital parts cannot be electrically isolated) Dane Oleson could partially show this in ROC measurements, and identify two parts: Digital to analog x-talk, independent of pulse hight X-talk component proportional to internal calibrate pulse  follow up needed to better understand/identify sources

Hans-Christian Kästli June 8, ROC internal X-talk (II) Sources for both types of x-talk identified –Analog x-talk: Parasitic capacitance parallel to injection capacitor, but bypassing calibrate enable switch Size compatible with observed behaviour Only layout change needed, easy to do –Digital x-talk: Parasitic coupling between power rails through N-well Very likely dominant effect, but want better quantitative understanding. Simulations ongoing. Need better/different decoupling of power rails –Other possible, but less dominant sources for x-talk identified. Will be improved anyway. Keep looking for other sources.

Hans-Christian Kästli June 8, Other issues / questions Lowering the absolute thresholds also lowers the in-time threshold –Nevertheless, can we further improve the in-time threshold? –Optimise timewalk behaviour of comparator In P5 we set the clock phase by doing a timing scan to find the efficiency plateau. A non-optimal setting reduces the allowed timewalk and lowers the in-time threshold –How uniform is this phase across a module? –Is there a need to adjust it per ROC? (Beware that this means mandatory additional calibration/commissioning work)