Digital 2 : EKT 221

Today’s Outline RTL Arithmetic Operations Conditional Register Transfer RTL Logical Operations RTL Shift Operations

Arithmetic Operations + Addition - Subtraction * Multiplication / Division Example:R2R1+R2 Example:R2R1+R2+1 Example:R2R1*R2 Example:R2R1/R2

Conditional Register Transfer Conditional Statement  Using control signal to control the transfer  Can be symbolized by if-then statement If (K 1 = 1) then (R2 R1)  In RTL we can write it as: K 1 : R2 R1 A subscripted letter followed by a colon is a conditional

Conditional Register Transfer R2 R1 K1K1 CLK n K1K1 Transfer occurs here n = no. of lines = no. of bits Transfer occurs in parallel K 1 : R2 R

Conditional Register Transfer Content of R2 will be stored in R5 when condition K 1 occurs: R5 R2 K K1 :R5 R2 Example:

COMPLEX LOGICAL SYMBOLS Content of R5 will be stored in R4 only IF both condition K1 and condition K2 are true: K1K2:R4R5

COMPLEX LOGICAL SYMBOLS Content of R5 were to be stored in R4 IF either condition K1 or condition K2 were true, a + sign would be used: (K1+K2) : R4 R5 NOTE: "+" (as in K1 + K2) means “OR.” In R1 ← R1 + R3, “+” means “plus.”

COMPLEX LOGICAL SYMBOLS If – then – else is implemented with commas and multiple colons. If K1 true, then stores R4 into R6, else if K2 true, then stores R5 into R6, else store R7 into R6. K1 : R6R4, K1K2 : R6 R5, K1K2: R6 R7

Summary Note : Any register may be specified for source 1, source 2, or destination.

Logical Operations v OR (SETS Bits) ^ AND (CLEARS Bits) + EXOR (Complement Bits, 2 Sources) NOT (Complement Bits, 1 Source) Example:R3R4 v R6 Example:R2DR ^ R1 Example:PCPC + DR Example:R6R1

Logical Operations Example: Let R1 = and R2 = After the operations, R0 becomes:

Shift Operations To Shift left and shift right operations:

Shift Operations Example 1: Let R2 = After the Shift operation, R1 becomes: Note: These shifts "zero fill". Sometimes a separate flip-flop is used to provide the data shifted in, or to “catch” the data shifted out

Shift Operations Example 2 : shift right operation P : R1 sl R1 If R1 = 1001, then sr R1 = 0010 R1 3 R1 2 R1 1 R1 0 0 P Zero Fill

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