Codelink Using Embedded Code for Verification Stimulus

Copyright © , Mentor Graphics.jpk Codelink March 05 2 Functional Verification of ICs & ASICs n On average 5.6 engineers spend 11 weeks developing and 9 weeks running directed tests n They write 267 tests and import/reuse 113 which detect 106 design errors n Yet 59% of designs fail first silicon and a functional flaw is the cause 90% of the time Source: Collett International 2005

Copyright © , Mentor Graphics.jpk Codelink March 05 3 Complex Designs and the Verification Gap * Source: SIA Roadmap 2001 Verification Gap Design Gap

Copyright © , Mentor Graphics.jpk Codelink March 05 4 Verification Methods n Directed Tests n Coverage Driven Verification (CDV) n Assertion-Based Verification (ABV)

Copyright © , Mentor Graphics.jpk Codelink March 05 5 Directed Tests Module being Verified StimulusResults Check

Copyright © , Mentor Graphics.jpk Codelink March 05 6 Coverage Driven Verification Module being Verified StimulusResults Check

Copyright © , Mentor Graphics.jpk Codelink March 05 7 ModelSim Code Coverage n Measures language coverage — Have you executed each: n Statement n Branch n Condition n Expression n Or Toggled each bit — Impossible to relate to functional specifications or test plans — Does not guarantee bug free n Best used at block level — Easier to exercise code aspects — Ensures blocks are tested & ready for integration n Built-in ModelSim — Low overhead — Easy to use

Copyright © , Mentor Graphics.jpk Codelink March 05 8 Assertion Based Verification Module being Verified StimulusResults Check

Copyright © , Mentor Graphics.jpk Codelink March In Assertion Based Verification System Interconnect 0 AMBA Bus DMA RAM Ethernet Controller SDRAM Controller SDRAM Encryption Engine PCI Bus PHY Powerful formal verification that targets Verification Hot Spots (80/20 Rule) checker Arbiter Multiple clock domains PCI Bridge μCμC μCμC PCI Bridge n Library of Standard Checkers — AMBA Bus Checker n Assertion Synthesis n Finds Verification “Hot Spots” — Focus on error prone areas

Copyright © , Mentor Graphics.jpk Codelink March Verification Requires Stimulus n ABV and CDV require dynamic simulations and stimulus — Directed Tests — Constrained Random Tests n For modules interacting with processors — Use embedded code to drive stimulus n Easy to create n Realistic stimulus

Copyright © , Mentor Graphics.jpk Codelink March Verification Strategy n Maximum Coverage, Minimum Simulation n Directed Tests — Basic coverage, corner conditions n Constrained Random Tests — Exercise unexpected combinations n Code as stimulus — Focus on typical system operation — Compliments ABV and CDV

Copyright © , Mentor Graphics.jpk Codelink March Codelink Usage Model n Early in the design Cycle — Used as a bus functional model n Middle of design Cycle — Generates AMBA stimulus for block level verification (BFM) — Can drive ABMA cycles as constrained random stimulus — Use small programs as directed module tests n Late in the design Cycle — Replaces full-functional model in regression tests where processor is present

Copyright © , Mentor Graphics.jpk Codelink March Codelink AMBA BFM Bool my_test(void) { unsigned char err; WriteByte(0x , 0xFF); WriteLong(0x , 0x ); while(ReadByte(0x )) { err = ReadByte(0x ); if (err == 0x1F) return FALSE; } return TRUE; }

Copyright © , Mentor Graphics.jpk Codelink March Constrained Random AMBA Traffic active = 80; idle = 20; cr_struct[] = { { 10, 0x , 0x0000FFFF, 4, {read_l, write_l}, {50, 50}}, { 30, 0x , 0x40000FFF, 8, {read_b, write_l}, {80, 20}}, { 60, 0x , 0x8003FFFF, 1, {read_b, write_b}, {35, 65}} }; n Compile into CR generator n Random Bus traffic is generated based on values in CR_struct n Address ranges can may overlap n Unlimited number of address ranges Percent of time bus will be activePercent of time bus will be idlePercent of time this address range will be accessedStart of Address RangeEnd of Address RangeBus Cycle AlignmentBus Cycles to DrivePercent of Cycles to Drive

Copyright © , Mentor Graphics.jpk Codelink March Types of Code n Small functions as directed tests — Specific module function — If you are using ARM’s DSM you are already doing this n Diagnostics — Exhaustively tests interfaces, some functionality n Driver code — Exhaustively tests functionality, some interface n Application Code — Tests typical operation Different Types of Code have different coverage profiles

Copyright © , Mentor Graphics.jpk Codelink March Improve Test Coverage with Software n Orthogonal view of design functionality — software is developed against the specification without detailed knowledge of the hardware n Real-world stimulus — Boot code — Hardware diagnostics — Device drivers n Used on first silicon, why not pre-tapeout? n It’s free stimulus (well, almost)

Copyright © , Mentor Graphics.jpk Codelink March Manually Linking Software with Simulation software Developer n Must convert software binary to memory image file n No source-level debug n Slow, ~ 1 to 10 instructions/sec Standards: VHDL, Verilog, SystemVerilog, PSL, SystemC Testbench Automation Coverage- Driven Verification Integrated Debug Environment Assertion- Based Verification System-Level Design Verification Engineer

Copyright © , Mentor Graphics.jpk Codelink March Codelink Automates Software Testbenches Codelink n Loads software binary n Full source-level debug n Significantly faster than full-functional model Standards: VHDL, Verilog, SystemVerilog, PSL, SystemC Testbench Automation Coverage- Driven Verification Integrated Debug Environment Assertion- Based Verification System-Level Design software Developer

Copyright © , Mentor Graphics.jpk Codelink March Codelink Benefits n Increase verification coverage with minimal effort n Simple for hardware engineer to use — Drive from ModelSim — No New GUI n Code is reusable in later design phases

Copyright © , Mentor Graphics.jpk Codelink March Codelink Setup n Instantiate Codelink ARM model n Invoke ModelSim, as usual n Point Codelink to the software object file n Specify code, data and stack memory ranges n Run ModelSim, as usual

Copyright © , Mentor Graphics.jpk Codelink March Codelink Setup Specify Memory Regions Driven from ModelSim Locate software executable

Copyright © , Mentor Graphics.jpk Codelink March Codelink Architecture Clock-Cycle Accurate ARM Processor Model Fast Access Memory Data Transfer & Steering Synchronization & Control Codelink Fast Access Memory supports 100K cycles/second Hardware I/O cycles run 1 to 10 cycles/second

Copyright © , Mentor Graphics.jpk Codelink March Source-Level Software Debug n Source & assembly level debug n Register & variable inspection n Invoke minimized if debug is not required

Copyright © , Mentor Graphics.jpk Codelink March Bus Cycles LDR R5, [R9]; -- Read ASIC Register LDR R3, [R10+FLUX]; -- Get flux const. ADD R3, R3, R5; -- Add flux capacitance AND R3, R3, [R10+MASK]; -- Mask out high bits SUB R3, R3, [R10+DIFF]; -- Subtract differential LDR R6, [R10+COSW]; -- Get Cosworth value XOR R3, R3, R6 -- Apply Cosworth filter ADD R9, R9, R4; -- Compute register offset STR R5, [R9]; -- Write Register HW READ HW WRITE FETCH HW READ FETCH DATA READ FETCH DATA READ FETCH DATA READ FETCH DATA READ FETCH HW WRITE

Copyright © , Mentor Graphics.jpk Codelink March Codelink Speeds Software Execution HW READ FETCH DATA READ FETCH DATA READ FETCH DATA READ FETCH DATA READ FETCH HW WRITE Traditional MethodCodelink Full Functional Model (DSM) Bus Interface Model Cycle Accurate Model Logic simulator ~10 cycles per second Logic simulator ~10 cycles per second ~100K cycles per second software

Copyright © , Mentor Graphics.jpk Codelink March Faster Simulation Waveform View Fetch I/OFetch ReadFetch ReadFetch ReadFetch ReadFetch I/O LDR R5, [R9]; -- Read ASIC Register LDR R3, [R10+FLUX]; -- Get flux const. ADD R3, R3, R5; -- Add flux capacitance AND R3, R3, [R10+MASK]; -- Mask out high bits SUB R3, R3, [R10+DIFF]; -- Subtract differential LDR R6, [R10+COSW]; -- Get Cosworth value XOR R3, R3, R6 -- Apply Cosworth filter ADD R9, R9, R4; -- Compute register offset STR R5, [R9]; -- Write Register

Copyright © , Mentor Graphics.jpk Codelink March Codelink Acceleration Factor n Codelink accelerates memory cycles n Ratio of memory to simulation cycles varies across phases of software execution Load RegistersUnload RegistersEvaluate ResultsPropagate Values Memory Intensive Memory ExclusiveSimulation Intensive 10x to 100x1x10x to 100x1,000x Codelink Acceleration Factor

Copyright © , Mentor Graphics.jpk Codelink March Codelink Summary n Improve chance of first silicon success — Enhance coverage without writing more tests n Simple setup and fast execution n Source-level software debug n Verify software prior to tapeout

Copyright © , Mentor Graphics.jpk Codelink March Codelink vs. Seamless n Codelink lacks the following Seamless features — Memory coherency — Performance profiler — Dynamic changes to memory optimizations — Denali license — Seamless GUI — Support for multiple processors — CBridge and SPI — Multiple invocations per license n Codelink — Works only with ModelSim and ARM PSPs

Copyright © , Mentor Graphics.jpk Codelink March Supported ARM Cores n ARM7tdmi n ARM926 n ARM946 n ARM966 n ARM1020 n ARM1022 n ARM1026 n ARM1136

Copyright © , Mentor Graphics.jpk Codelink March What Code to Run? n Different types of code have different coverage profiles n Diagnostics — Exhaustive connectivity, limited functionality n Driver Code — Exhaustive functionality, limited connectivity n Application Code — Typical operation

Copyright © , Mentor Graphics.jpk Codelink March Directed Tests Module being Verified TestBench

Copyright © , Mentor Graphics.jpk Codelink March Focus on Typical Operation n Code lets you focus more verification on typical system operation, which is where bugs will be found by users in actual operation

Copyright © , Mentor Graphics.jpk Codelink March Simulation Isn’t Always Enough System Interconnect 0System Interconnect 1 DMA RAM PCI Bridge Ethernet Controller SDRAM Controller SDRAM μCμC Encryption Engine PCI Bus PHY Static Formal Verification Exhaustive Dynamic Formal Verification Locally exhaustive Powerful formal verification that targets Verification Hot Spots (80/20 Rule) simulation test case checker corner case Arbiter Multiple clock domains