Veljko Milutinović Saša Stojanović University of Belgrade 1.

Slides:

Advertisements

Similar presentations

Chapter 1. Basic Structure of Computers

Advertisements

A Digital Circuit Toolbox

 SMALL  50  BIG  100 ANTE 0 End NEXT LEVEL

©2004 Brooks/Cole FIGURES FOR CHAPTER 9 MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES Click the mouse to move to the next page. Use the ESC key.

1 CDSC CHP Prototyping Yu-Ting Chen, Jason Cong, Mohammad Ali Ghodrat, Muhuan Huang, Chunyue Liu, Bingjun Xiao, Yi Zou.

Final Class, ECE472 Midterm #2 due today – 1-5% extra credit for written report of Dally’s video Oral presentation of class project: today Graduate students:

Extensible Processors. 2 ASIP Gain performance by:  Specialized hardware for the whole application (ASIC). −  Almost no flexibility. −High cost.  Use.

Introduction to Reconfigurable Computing CS61c sp06 Lecture (5/5/06) Hayden So.

1 Chapter 14 Embedded Processing Cores. 2 Overview RISC: Reduced Instruction Set Computer RISC-based processor: PowerPC, ARM and MIPS The embedded processor.

Murali Vijayaraghavan MIT Computer Science and Artificial Intelligence Laboratory RAMP Retreat, UC Berkeley, January 11, 2007 A Shared.

1 Sec (2.3) Program Execution. 2 In the CPU we have CU and ALU, in CU there are two special purpose registers: 1. Instruction Register 2. Program Counter.

The CPU The Central Presentation Unit Language Levels Fetch execute cycle Processor speed.

A-Level Computing#BristolMet Session Objectives#4 MUST describe the differences between the main types of primary memory SHOULD describe the function and.

ALTERA UP2 Tutorial 1: The 15 Minute Design. Figure 1.1 The Altera UP 1 CPLD development board. ALTERA UP2 Tutorial 1: The 15 Minute Design.

Lecture 13 - Introduction to the Central Processing Unit (CPU)

V. Milutinović, G. Rakocevic, S. Stojanović, and Z. Sustran University of Belgrade Oskar Mencer Imperial College, London Oliver Pell Maxeler Technologies,

V. Milutinović, G. Rakocevic, S. Stojanović, and Z. Sustran University of Belgrade Oskar Mencer Imperial College, London Oliver Pell Maxeler Technologies,

EKT303/4 PRINCIPLES OF PRINCIPLES OF COMPUTER ARCHITECTURE (PoCA)

Veljko Milutinović VLSI for SuperComputing: From Applications and Algorithms to Masks and Chips 1/40.

Computer Science, Software Engineering & Robotics Workshop, FGCU, April 27-28, 2012 FPGA: Field Programmable Gate Arrays Vincent Giannone Mentor: Dr. Janusz.

Detecting software clones in binaries Zaharije Radivojević, Saša Stojanović, Miloš Cvetanović School of Electrical Engineering, Belgrade University 14th.

Veljko Milutinović and Saša Stojanović University of Belgrade Oliver Pell and Oskar Mencer Maxeler Technologies 1.

V. Milutinovic, G. Rakocevic, S. Stojanovic, and Z. Sustran University of Belgrade Oskar Mencer Imperial College, London Oliver Pell Maxeler Technologies,

Chapter One Understanding Computer Hardware Part I: Processors.

Enabling Multi-threaded Applications on Hybrid Shared Memory Manycore Architectures Tushar Rawat and Aviral Shrivastava Arizona State University, USA CML.

CSE 494: Electronic Design Automation Lecture 2 VLSI Design, Physical Design Automation, Design Styles.

Micro-Research Finland Oy Components for Integrating Device Controllers for Fast Orbit Feedback Jukka Pietarinen EPICS Collaboration Meeting Knoxville.

V. Milutinović, G. Rakocevic, S. Stojanović, and Z. Sustran University of Belgrade Oskar Mencer Imperial College, London Oliver Pell Maxeler Technologies.

© 2008 Altera Corporation High-Quality, Deterministic Parallel Placement for FPGAs on Commodity Hardware Adrian Ludwin, Vaughn Betz and Ketan Padalia.

V. Milutinović, G. Rakocevic, S. Stojanović, and Z. Sustran University of Belgrade Oskar Mencer Imperial College, London Oliver Pell Maxeler Technologies,

Digital System Design Verilog ® HDL Introduction to Synthesis: Concepts and Flow Maziar Goudarzi.

Free Phone $25 a month 100 minutes then 35c per min Free Phone $25 a month 100 minutes then 35c per min Free Phone $20 a month 75 minutes then 25c per.

Parallel Portability and Heterogeneous programming Stefan Möhl, Co-founder, CSO, Mitrionics.

CEC 220 Digital Circuit Design Programmable Logic Devices

Sasa Stojanovic Veljko Milutinovic

Scaling up from local DB to distributed DB Cristiano Bozza European Emulsion Group Nagoya, Jan 2004 Presented by Giuseppe Grella.

Using software metrics for estimating code similarities in binaries Saša Stojanović, Miloš Cvetanović, Zaharije Radivojević School of Electrical Engineering,

Control Unit Operations Chapter10:. What is Control Unit (CU)?(1)  Part of a CPU or other device that directs its operation.  Tells the rest of the.

Page 1/8 Introduction to Maxeler Computing Veljko Milutinovic,

Internal Logic Analyzer Characterization presentation By: Moran Katz and Zvika Pery Mentor: Moshe Porian Dual-semester project Spring 2012.

FPGA ( Field programmable gate array ) April 2008 Prepared by : Muhammad Ziyada Muhammad Al tabakh.

Types of Micro-operation  Transfer data between registers  Transfer data from register to external  Transfer data from external to register  Perform.

A computer consists of five functionally independent main parts.

Computer Applications in Business

Interpreted languages Jakub Yaghob

CA Final Project – Multithreaded Processor with IPC Interface

This chapter in the book includes: Objectives Study Guide

ZCU102 (Xilinx Zynq Ultrascale+

LESSON 1 Introduction to Programming Language

Introduction to Programmable Logic

Introduction to Maxeler Computing Veljko Milutinovic,

Head-to-Head Xilinx Virtex-II Pro Altera Stratix 1.5v 130nm copper

Genomic Data Clustering on FPGAs for Compression

A unified instruction and data cache

With Thermal Code inputs

ELEN 468 Advanced Logic Design

EE345: Introduction to Microcontrollers Memory

المدخل إلى تكنولوجيا التعليم في ضوء الاتجاهات الحديثة

15 seconds left 30 seconds left 3 minutes left 2 minutes left 1 minute

Computers: Tools for an Information Age

The Big 6 Research Model Step 3: Location and Access

EE 193: Parallel Computing

Programmable Logic- How do they do that?

ECE 545 Remaining Tasks.

Exploring Application Specific Programmable Logic Devices

EE 155 / Comp 122 Parallel Computing

Computers: Tools for an Information Age

Sec (2.3) Program Execution.

Computer Science. The CPU The CPU is made up of 3 main parts : Cache ALU Control Unit.

Presentation transcript:

Veljko Milutinović Saša Stojanović University of Belgrade 1

DualCore? Where are the horses going? 2

Is it possible to use 2000 chicken instead of two horses? ? == 3

2 x 1000 chickens 4

How about ants? 5 Data

Marmalade Big Data Input Results 6

Factor: 20 to 200 MultiCore/ManyCoreDataFlow Machine Level Code Gate Transfer Level 7

Factor: 20 MultiCore/ManyCoreDataFlow 8 P = C*U 2 *f

Factor: 20 Data Processing Process Control Data Processing Process Control MultiCore/ManyCoreDataFlow

MultiCore: Explain what to do, to the driver Caches, instruction buffers, and predictors needed ManyCore: Explain what to do, to many sub-drivers Reduced caches and instruction buffers needed DataFlow: No caches, instruction buffers, or predictors needed: C min Make a field of processing gates: +5 Java programs 10

MultiCore: Business as usual ManyCore: More difficult DataFlow: Much more difficult Debugging both, application and configuration code: 5 Java + C min 11

MultiCore/ManyCore: Several minutes DataFlow: Several hours (to configure the FPGA structures) Future: Xilinx, Altera, Achronix (UCB 1GHz), Tabula (MIT, 1.6GHz) 12

13

MultiCore: Horse stable ManyCore: Chicken house DataFlow: Ant hole 14

MultiCore: Haystack ManyCore: Cornbits DataFlow: Crumbs 15

16 Small Data

17 Medium Data

18 Big Data

19