Data Flow Modeling of Combinational Logic Simple Testbenches ECE 448 Lecture 3 Data Flow Modeling of Combinational Logic Simple Testbenches ECE 448 – FPGA and ASIC Design with VHDL

Required reading S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design Chapter 6, Combinational-Circuit Building Blocks (sections 6.6.5-6.6.7 optional) Chapter 5.5, Design of Arithmetic Circuits Using CAD Tools ECE 448 – FPGA and ASIC Design with VHDL

Optional Reading Sundar Rajan, Essential VHDL: RTL Synthesis Done Right Chapter 3, Gates, Decoders and Encoders (see errata at http://www.vahana.com/bugs.htm) ECE 448 – FPGA and ASIC Design with VHDL

Recommended reading Material covered next week and required during the second lab experiment S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design Chapter 7, Flip-Flops, Registers, Counters, and a Simple Processor (7.14 optional) ECE 448 – FPGA and ASIC Design with VHDL

VHDL Design Styles ECE 448 – FPGA and ASIC Design with VHDL

VHDL Design Styles VHDL Design Styles dataflow structural behavioral Testbenches dataflow structural behavioral Concurrent statements Components and interconnects Sequential statements Registers State machines Subset most suitable for synthesis ECE 448 – FPGA and ASIC Design with VHDL

xor3 Example ECE 448 – FPGA and ASIC Design with VHDL

Entity xor3 LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY xor3 IS PORT( A : IN STD_LOGIC; B : IN STD_LOGIC; C : IN STD_LOGIC; Result : OUT STD_LOGIC ); end xor3 ; ECE 448 – FPGA and ASIC Design with VHDL

Dataflow Architecture (xor3 gate) ARCHITECTURE dataflow OF xor3 IS SIGNAL U1_OUT: STD_LOGIC; BEGIN U1_OUT <= A XOR B; Result <= U1_OUT XOR C; END dataflow; U1_OUT ECE 448 – FPGA and ASIC Design with VHDL

Dataflow Description Describes how data moves through the system and the various processing steps. Data Flow uses series of concurrent statements to realize logic. Concurrent statements are evaluated at the same time; thus, order of these statements doesn’t matter. Data Flow is most useful style when series of Boolean equations can represent a logic. ECE 448 – FPGA and ASIC Design with VHDL

Structural Architecture (xor3 gate) ARCHITECTURE structural OF xor3 IS SIGNAL U1_OUT: STD_LOGIC; COMPONENT xor2 PORT( I1 : IN STD_LOGIC; I2 : IN STD_LOGIC; Y : OUT STD_LOGIC ); END COMPONENT; BEGIN U1: xor2 PORT MAP (I1 => A, I2 => B, Y => U1_OUT); U2: xor2 PORT MAP (I1 => U1_OUT, I2 => C, Y => Result); END structural; A B xor3 Result C U1_OUT I1 I2 Y I1 I2 Y ECE 448 – FPGA and ASIC Design with VHDL

xor2 xor2.vhd LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY xor2 IS PORT( I1 : IN STD_LOGIC; I2 : IN STD_LOGIC; Y : OUT STD_LOGIC); END xor2; ARCHITECTURE dataflow OF xor2 IS BEGIN Y <= I1 xor I2; END dataflow; ECE 448 – FPGA and ASIC Design with VHDL

Structural Description Structural design is the simplest to understand. This style is the closest to schematic capture and utilizes simple building blocks to compose logic functions. Components are interconnected in a hierarchical manner. Structural descriptions may connect simple gates or complex, abstract components. Structural style is useful when expressing a design that is naturally composed of sub-blocks. ECE 448 – FPGA and ASIC Design with VHDL

Behavioral Architecture (xor3 gate) ARCHITECTURE behavioral OF xor3 IS BEGIN xor3_behave: PROCESS (A,B,C) IF ((A XOR B XOR C) = '1') THEN Result <= '1'; ELSE Result <= '0'; END IF; END PROCESS xor3_behave; END behavioral; ECE 448 – FPGA and ASIC Design with VHDL

Behavioral Description It accurately models what happens on the inputs and outputs of the black box (no matter what is inside and how it works). This style uses PROCESS statements in VHDL. ECE 448 – FPGA and ASIC Design with VHDL

Describing Combinational Logic Using Dataflow Design Style ECE 448 – FPGA and ASIC Design with VHDL

Register Transfer Level (RTL) Design Description Today’s Topic Combinational Logic Combinational Logic … Registers ECE 448 – FPGA and ASIC Design with VHDL

VHDL Design Styles VHDL Design Styles dataflow structural behavioral Testbenches dataflow structural behavioral Concurrent statements Components and interconnects Sequential statements Registers State machines Subset most suitable for synthesis ECE 448 – FPGA and ASIC Design with VHDL

Synthesizable VHDL Dataflow VHDL Design Style VHDL code synthesizable ECE 448 – FPGA and ASIC Design with VHDL

Concurrent statements Data-flow VHDL Major instructions Concurrent statements concurrent signal assignment () conditional concurrent signal assignment (when-else) selected concurrent signal assignment (with-select-when) generate scheme for equations (for-generate) ECE 448 – FPGA and ASIC Design with VHDL

Concurrent statements Data-flow VHDL Major instructions Concurrent statements concurrent signal assignment () conditional concurrent signal assignment (when-else) selected concurrent signal assignment (with-select-when) generate scheme for equations (for-generate) ECE 448 – FPGA and ASIC Design with VHDL

Data-flow VHDL: Example ECE 448 – FPGA and ASIC Design with VHDL

Data-flow VHDL: Example (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY fulladd IS PORT ( x : IN STD_LOGIC ; y : IN STD_LOGIC ; cin : IN STD_LOGIC ; s : OUT STD_LOGIC ; cout : OUT STD_LOGIC ) ; END fulladd ; ECE 448 – FPGA and ASIC Design with VHDL

Data-flow VHDL: Example (2) ARCHITECTURE dataflow OF fulladd IS BEGIN s <= x XOR y XOR cin ; cout <= (x AND y) OR (cin AND x) OR (cin AND y) ; END dataflow ; ECE 448 – FPGA and ASIC Design with VHDL

Logic Operators Logic operators Logic operators precedence and or nand nor xor not xnor only in VHDL-93 Highest No order precedents not and or nand nor xor xnor Lowest ECE 448 – FPGA and ASIC Design with VHDL

No Implied Precedence Wanted: y = ab + cd Incorrect y <= a and b or c and d ; equivalent to y <= ((a and b) or c) and d ; y = (ab + c)d Correct y <= (a and b) or (c and d) ; No order precedents ECE 448 – FPGA and ASIC Design with VHDL

Arithmetic Operators in VHDL (1) To use basic arithmetic operations involving std_logic_vectors you need to include the following library packages: LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; or USE ieee.std_logic_signed.all; Internal signals are from DUT. Main process may be split into main process. I.e. one to drive clk, rst and other for test vectors. Many architectures can be tested by inserting more for DUT:TestComp use entity work.TestComp(archName) statmetns “work” is the name of the library that “TestComp” is being compiled to. The “DUT” tag is required. ECE 448 – FPGA and ASIC Design with VHDL

Arithmetic Operators in VHDL (2) You can use standard +, -, * operators to perform addition and subtraction: signal A : STD_LOGIC_VECTOR(3 downto 0); signal B : STD_LOGIC_VECTOR(3 downto 0); signal C : STD_LOGIC_VECTOR(3 downto 0); …… C <= A + B; Internal signals are from DUT. Main process may be split into main process. I.e. one to drive clk, rst and other for test vectors. Many architectures can be tested by inserting more for DUT:TestComp use entity work.TestComp(archName) statmetns “work” is the name of the library that “TestComp” is being compiled to. The “DUT” tag is required. ECE 448 – FPGA and ASIC Design with VHDL

16-bit Unsigned Adder X Y Cout Cin S 16 16 16 ECE 448 – FPGA and ASIC Design with VHDL

VHDL code for a 16-bit Unsigned Adder LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_unsigned.all ; ENTITY adder16 IS PORT ( Cin : IN STD_LOGIC ; X, Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ; S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ; Cout : OUT STD_LOGIC ) ; END adder16 ; ARCHITECTURE dataflow OF adder16 IS SIGNAL Sum : STD_LOGIC_VECTOR(16 DOWNTO 0) ; BEGIN Sum <= ('0' & X) + Y + Cin ; S <= Sum(15 DOWNTO 0) ; Cout <= Sum(16) ; END dataflow ; ECE 448 – FPGA and ASIC Design with VHDL

Concurrent statements Data-flow VHDL Major instructions Concurrent statements concurrent signal assignment () conditional concurrent signal assignment (when-else) selected concurrent signal assignment (with-select-when) generate scheme for equations (for-generate) ECE 448 – FPGA and ASIC Design with VHDL

Conditional concurrent signal assignment When - Else target_signal <= value1 when condition1 else value2 when condition2 else . . . valueN-1 when conditionN-1 else valueN; ECE 448 – FPGA and ASIC Design with VHDL

Most often implied structure When - Else target_signal <= value1 when condition1 else value2 when condition2 else . . . valueN-1 when conditionN-1 else valueN; Value N Value N-1 Condition N-1 Condition 2 Condition 1 Value 2 Value 1 Target Signal … 1 .… 1 1 ECE 448 – FPGA and ASIC Design with VHDL

Operators Relational operators Logic and relational operators precedence = /= < <= > >= Highest not = /= < <= > >= and or nand nor xor xnor No order precedents Lowest ECE 448 – FPGA and ASIC Design with VHDL

Priority of logic and relational operators compare a = bc Incorrect … when a = b and c else … equivalent to … when (a = b) and c else … Correct … when a = (b and c) else … No order precedents ECE 448 – FPGA and ASIC Design with VHDL

VHDL operators ECE 448 – FPGA and ASIC Design with VHDL

2-to-1 Multiplexer s f s w w f w 1 1 w 1 1 (a) Graphical symbol w f w 1 1 1 w 1 (a) Graphical symbol (b) Truth table ECE 448 – FPGA and ASIC Design with VHDL

VHDL code for a 2-to-1 Multiplexer LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux2to1 IS PORT ( w0, w1, s : IN STD_LOGIC ; f : OUT STD_LOGIC ) ; END mux2to1 ; ARCHITECTURE dataflow OF mux2to1 IS BEGIN f <= w0 WHEN s = '0' ELSE w1 ; END dataflow ; ECE 448 – FPGA and ASIC Design with VHDL

Cascade of two multiplexers 3 w 1 y 2 w 1 1 s2 s1 ECE 448 – FPGA and ASIC Design with VHDL

VHDL code for a cascade of two multiplexers LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux_cascade IS PORT ( w1, w2, w3: IN STD_LOGIC ; s1, s2 : IN STD_LOGIC ; f : OUT STD_LOGIC ) ; END mux_cascade ; ARCHITECTURE dataflow OF mux2to1 IS BEGIN f <= w1 WHEN s1 = ‘1' ELSE w2 WHEN s2 = ‘1’ ELSE w3 ; END dataflow ; ECE 448 – FPGA and ASIC Design with VHDL

Other examples of use of conditional concurrent signal assignment (when-else) ECE 448 – FPGA and ASIC Design with VHDL

Tri-state Buffer – example (1) LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY tri_state IS PORT ( ena: IN STD_LOGIC; input: IN STD_LOGIC; output: OUT STD_LOGIC ); END tri_state; ECE 448 – FPGA and ASIC Design with VHDL

Tri-state Buffer – example (2) ARCHITECTURE dataflow OF tri_state IS BEGIN output <= input WHEN (ena = ‘0’) ELSE ‘Z’; END dataflow; ECE 448 – FPGA and ASIC Design with VHDL

4-bit Number Comparator AeqB AgtB 4 B AltB ECE 448 – FPGA and ASIC Design with VHDL

VHDL code for a 4-bit Unsigned Number Comparator LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_unsigned.all ; ENTITY compare IS PORT ( A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; AeqB, AgtB, AltB : OUT STD_LOGIC ) ; END compare ; ARCHITECTURE dataflow OF compare IS BEGIN AeqB <= '1' WHEN A = B ELSE '0' ; AgtB <= '1' WHEN A > B ELSE '0' ; AltB <= '1' WHEN A < B ELSE '0' ; END dataflow ; ECE 448 – FPGA and ASIC Design with VHDL

VHDL code for a 4-bit Signed Number Comparator LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_signed.all ; ENTITY compare IS PORT ( A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; AeqB, AgtB, AltB : OUT STD_LOGIC ) ; END compare ; ARCHITECTURE dataflow OF compare IS BEGIN AeqB <= '1' WHEN A = B ELSE '0' ; AgtB <= '1' WHEN A > B ELSE '0' ; AltB <= '1' WHEN A < B ELSE '0' ; END dataflow ; ECE 448 – FPGA and ASIC Design with VHDL

Priority Encoder d 1 w y z x w y w y w z w 2 3 1 1 2 3 y w 1 y 1 w 2 z w 3 d 1 w y z x 2 3 ECE 448 – FPGA and ASIC Design with VHDL

VHDL code for a Priority Encoder LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY priority IS PORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ; z : OUT STD_LOGIC ) ; END priority ; ARCHITECTURE dataflow OF priority IS BEGIN y <= "11" WHEN w(3) = '1' ELSE "10" WHEN w(2) = '1' ELSE "01" WHEN w(1) = '1' ELSE "00" ; z <= '0' WHEN w = "0000" ELSE '1' ; END dataflow ; ECE 448 – FPGA and ASIC Design with VHDL

Concurrent statements Data-flow VHDL Major instructions Concurrent statements concurrent signal assignment () conditional concurrent signal assignment (when-else) selected concurrent signal assignment (with-select-when) generate scheme for equations (for-generate) ECE 448 – FPGA and ASIC Design with VHDL

Selected concurrent signal assignment With –Select-When with choice_expression select target_signal <= expression1 when choices_1, expression2 when choices_2, . . . expressionN when choices_N; ECE 448 – FPGA and ASIC Design with VHDL

Most Often Implied Structure With –Select-When with choice_expression select target_signal <= expression1 when choices_1, expression2 when choices_2, . . . expressionN when choices_N; expression1 choices_1 expression2 choices_2 target_signal expressionN choices_N choice expression ECE 448 – FPGA and ASIC Design with VHDL

Allowed formats of choices_k WHEN value WHEN value_1 | value_2 | .... | value N WHEN OTHERS ECE 448 – FPGA and ASIC Design with VHDL

Allowed formats of choice_k - example WITH sel SELECT y <= a WHEN "000", c WHEN "001" | "111", d WHEN OTHERS; ECE 448 – FPGA and ASIC Design with VHDL

4-to-1 Multiplexer s s s s f 1 1 w 00 w w 01 1 1 w f 1 w 10 2 1 w 2 w s s s f 1 1 w 00 w w 01 1 1 w f 1 w 10 2 1 w 2 w 11 3 1 1 w 3 (a) Graphic symbol (b) Truth table ECE 448 – FPGA and ASIC Design with VHDL

VHDL code for a 4-to-1 Multiplexer LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux4to1 IS PORT ( w0, w1, w2, w3 : IN STD_LOGIC ; s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; f : OUT STD_LOGIC ) ; END mux4to1 ; ARCHITECTURE dataflow OF mux4to1 IS BEGIN WITH s SELECT f <= w0 WHEN "00", w1 WHEN "01", w2 WHEN "10", w3 WHEN OTHERS ; END dataflow ; ECE 448 – FPGA and ASIC Design with VHDL

Other examples of use of selected concurrent signal assignment (with-select-when) ECE 448 – FPGA and ASIC Design with VHDL

2-to-4 Decoder En w w y y y y 1 1 2 3 w y 1 1 w y 1 1 1 1 1 y 1 1 1 2 1 2 3 w y 1 1 w y 1 1 1 1 1 y 1 1 1 2 y En 1 1 1 1 3 x x (a) Truth table (b) Graphical symbol ECE 448 – FPGA and ASIC Design with VHDL

VHDL code for a 2-to-4 Decoder LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY dec2to4 IS PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ; END dec2to4 ; ARCHITECTURE dataflow OF dec2to4 IS SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ; BEGIN Enw <= En & w ; WITH Enw SELECT y <= "1000" WHEN "100", "0100" WHEN "101", "0010" WHEN "110", "0001" WHEN "111", "0000" WHEN OTHERS ; END dataflow ; ECE 448 – FPGA and ASIC Design with VHDL

MLU Example ECE 448 – FPGA and ASIC Design with VHDL

MLU: Block Diagram ECE 448 – FPGA and ASIC Design with VHDL

MLU: Entity Declaration LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY mlu IS PORT( NEG_A : IN STD_LOGIC; NEG_B : IN STD_LOGIC; NEG_Y : IN STD_LOGIC; A : IN STD_LOGIC; B : IN STD_LOGIC; L1 : IN STD_LOGIC; L0 : IN STD_LOGIC; Y : OUT STD_LOGIC ); END mlu; ECE 448 – FPGA and ASIC Design with VHDL

MLU: Architecture Declarative Section ARCHITECTURE mlu_dataflow OF mlu IS SIGNAL A1 : STD_LOGIC; SIGNAL B1 : STD_LOGIC; SIGNAL Y1 : STD_LOGIC; SIGNAL MUX_0 : STD_LOGIC; SIGNAL MUX_1 : STD_LOGIC; SIGNAL MUX_2 : STD_LOGIC; SIGNAL MUX_3 : STD_LOGIC; SIGNAL L: STD_LOGIC_VECTOR(1 DOWNTO 0); ECE 448 – FPGA and ASIC Design with VHDL

MLU - Architecture Body BEGIN A1<= NOT A WHEN (NEG_A='1') ELSE A; B1<= NOT B WHEN (NEG_B='1') ELSE B; Y <= NOT Y1 WHEN (NEG_Y='1') ELSE Y1; MUX_0 <= A1 AND B1; MUX_1 <= A1 OR B1; MUX_2 <= A1 XOR B1; MUX_3 <= A1 XNOR B1; L <= L1 & L0; with (L) select Y1 <= MUX_0 WHEN "00", MUX_1 WHEN "01", MUX_2 WHEN "10", MUX_3 WHEN OTHERS; END mlu_dataflow; ECE 448 – FPGA and ASIC Design with VHDL

Behavioral Design Style for Testbenches ECE 448 – FPGA and ASIC Design with VHDL

VHDL Design Styles VHDL Design Styles dataflow structural behavioral Concurrent statements Components and interconnects Sequential statements Testbenches ECE 448 – FPGA and ASIC Design with VHDL

What is a PROCESS? A process is a sequence of instructions referred to as sequential statements. The Keyword PROCESS A process can be given a unique name using an optional LABEL This is followed by the keyword PROCESS The keyword BEGIN is used to indicate the start of the process All statements within the process are executed SEQUENTIALLY. Hence, order of statements is important. A process must end with the keywords END PROCESS. TESTING: process begin TEST_VECTOR<=“00”; wait for 10 ns; TEST_VECTOR<=“01”; TEST_VECTOR<=“10”; TEST_VECTOR<=“11”; end process; ECE 448 – FPGA and ASIC Design with VHDL

Execution of statements in a PROCESS Testing: PROCESS BEGIN test_vector<=“00”; WAIT FOR 10 ns; test_vector<=“01”; test_vector<=“10”; test_vector<=“11”; END PROCESS; The execution of statements continues sequentially till the last statement in the process. After execution of the last statement, the control is again passed to the beginning of the process. Order of execution Program control is passed to the first statement after BEGIN ECE 448 – FPGA and ASIC Design with VHDL

PROCESS with a WAIT Statement The last statement in the PROCESS is a WAIT instead of WAIT FOR 10 ns. This will cause the PROCESS to suspend indefinitely when the WAIT statement is executed. This form of WAIT can be used in a process included in a testbench when all possible combinations of inputs have been tested or a non-periodical signal has to be generated. Testing: PROCESS BEGIN test_vector<=“00”; WAIT FOR 10 ns; test_vector<=“01”; test_vector<=“10”; test_vector<=“11”; WAIT; END PROCESS; Order of execution Program execution stops here ECE 448 – FPGA and ASIC Design with VHDL

WAIT FOR vs. WAIT WAIT FOR: waveform will keep repeating itself forever … 1 2 3 1 2 3 WAIT : waveform will keep its state after the last wait instruction. … ECE 448 – FPGA and ASIC Design with VHDL

Simple Testbenches ECE 448 – FPGA and ASIC Design with VHDL

Generating selected values of one input SIGNAL test_vector : STD_LOGIC_VECTOR(2 downto 0); BEGIN ....... testing: PROCESS test_vector <= "000"; WAIT FOR 10 ns; test_vector <= "001"; test_vector <= "010"; test_vector <= "011"; test_vector <= "100"; END PROCESS; ........ END behavioral; ECE 448 – FPGA and ASIC Design with VHDL

Generating all values of one input SIGNAL test_vector : STD_LOGIC_VECTOR(3 downto 0):="0000"; BEGIN ....... testing: PROCESS WAIT FOR 10 ns; test_vector <= test_vector + 1; end process TESTING; ........ END behavioral; ECE 448 – FPGA and ASIC Design with VHDL

Generating all possible values of two inputs SIGNAL test_ab : STD_LOGIC_VECTOR(1 downto 0); SIGNAL test_sel : STD_LOGIC_VECTOR(1 downto 0); BEGIN ....... double_loop: PROCESS test_ab <="00"; test_sel <="00"; for I in 0 to 3 loop for J in 0 to 3 loop wait for 10 ns; test_ab <= test_ab + 1; end loop; test_sel <= test_sel + 1; END PROCESS; ........ END behavioral; ECE 448 – FPGA and ASIC Design with VHDL

Generating periodical signals, such as clocks CONSTANT clk1_period : TIME := 20 ns; CONSTANT clk2_period : TIME := 200 ns; SIGNAL clk1 : STD_LOGIC; SIGNAL clk2 : STD_LOGIC := ‘0’; BEGIN ....... clk1_generator: PROCESS clk1 <= ‘0’; WAIT FOR clk1_period/2; clk1 <= ‘1’; END PROCESS; clk2 <= not clk2 after clk2_period/2; END behavioral; ECE 448 – FPGA and ASIC Design with VHDL

Generating one-time signals, such as resets CONSTANT reset1_width : TIME := 100 ns; CONSTANT reset2_width : TIME := 150 ns; SIGNAL reset1 : STD_LOGIC; SIGNAL reset2 : STD_LOGIC := ‘1’; BEGIN ....... reset1_generator: PROCESS reset1 <= ‘1’; WAIT FOR reset_width; reset1 <= ‘0’; WAIT; END PROCESS; reset2_generator: PROCESS reset2 <= ‘0’; END behavioral; ECE 448 – FPGA and ASIC Design with VHDL

Typical error SIGNAL test_vector : STD_LOGIC_VECTOR(2 downto 0); SIGNAL reset : STD_LOGIC; BEGIN ....... generator1: PROCESS reset <= ‘1’; WAIT FOR 100 ns reset <= ‘0’; test_vector <="000"; WAIT; END PROCESS; generator2: PROCESS WAIT FOR 200 ns test_vector <="001"; WAIT FOR 600 ns test_vector <="011"; END behavioral; ECE 448 – FPGA and ASIC Design with VHDL