Programmable Logic Architecture Verilog HDL FPGA Design Jason Tseng Week 5

Abstract Today’s class:  Data-flow modeling  Examples

Data-Flow Modelling-Operators Arithmetic operators: –Operators: ‘+’::= addition, ‘-’::=subtraction, ‘*’::= multiplication, ‘/’::= division, ‘%’::=modulus. –Example: parameter n=4; reg [3:0] a, b, f, g, count; f=a+c; g=c-n; count=(count+1)%16 //count 0 through 15 Relational operators: –Compare two operands and return a single bit 1 or 0 –Operators: ‘ ’::= greater than, ‘>=’::= greater than or equal to, ‘==‘::= equal to, ‘!=‘::= not equal to. –Example: if (x==y) e=1; else e=0; // equivalent to e = (x==y)

Data-Flow Modelling-Operators Bit-wise operators: –A bit-by-bit comparison between two operands and return an operand vector –Operators: ‘~’::= bitwise NOT, ‘&’::= bitwise AND, ‘|’::= bitwise OR, ‘^’::= bitwise XOR, ‘~^’ or ‘^~’::= bitwise XNOR. –Example: module bit_wise_test(a,b,c); input[1:0] a,b; output[1:0] c; assign c = (a&b); // return c[0], c[1 c = (s) ? b:c; // condition expression of bitwise endmodule

Data-Flow Modelling-Operators Reduction operators: –Operate on all the bits of an operand vector (compare to all elements of a bus variable) and return a single-bit value. –These are unary (one argument) form of the bit-wise operators. –Operators: ‘&’::= reduction AND, ‘|’::= reduction OR, ‘~&’::= reduction NAND, ‘~|’::= reduction NOR, ‘^’::= reduction XOR, ‘~^’ or ‘^~’:: XNOR. –Example: module chk_zero(a,z); input [2:0] a; // an input bus output z; // a single output variable assign z = ~| a; // reduction NOR, z=1 for a=000 endmodule

Data-Flow Modelling-Operators Logical operators: –Return a single bit 1 or 0. They are the same as bit-wise operators but is applied only for single bit operands. –Operators: ‘!’::= logical NOT, ‘&&’::= logical AND, ‘||’::= logical OR. –Example: wire [7:0] x, y, z; // declare multi-bit variables reg a; …….. if ((x==y) && (z)) a=1; // a=1 if x equals y, and z is nonzero else a =(!x); // a=0 if x is anything but zero.

Data-Flow Modelling-Operators Shift operators: –Shift the first operand by the number of bits specified by the second operand. –Vacated positions are filled with zeros for both left and right shifts. –Operators: ‘ >’::= shift right –Example: assign c = a<<2; /* c=a shifted left for 2 bits; vacant positions are filled with 0’s */ e.g., a=6’b  c=6’b100100

Data-Flow Modelling-Operators Concatenation operator: – Combine two or more operands to form a larger vector. – Operator: ‘{}’::= concatenation. – Example: {a,b[3:1],4’b0110,c} equivalent to {a,b[3],b[2],b[1],1’b0,1’b1,1’b1,1’b0,c}. Replication operator: – Make multiple copies of an item. – Operator: ‘{n{item}}’::= n fold replication of an item. – Example: a={4{2’b01}} equivalent to a=8’b w={a,2{a,b,c}} equivalent to w={a,a,b,c,a,b,c}

Data-Flow Modelling-Operators Conditional operator: – Evaluate one of the two expression based on a condition. It will synthesize to a multiplexer (MUX). – Operator: (cond)?(result if cond true) : result if cond false) – Examples: assign a=(g) ? y1 : y2; /* if (g) then a=y1 else a=y2 if g=(x or z), then (bitwise) a=0 if y1=y2=0, or a=1 if y1=y2=1 else a=x */ assign a=(inc==2) ? a+1:a-1; /* if inc=2, then a=a+1 else a=a-1 */

4-bit comparator: bit-wise operator

Check even parity and all zeros using bit-wise operator XOR and XNOR

A parity bit is a bit that is added to ensure that the number ofbit bits with value of one in a given set of bits is always even oroneeven odd. Parity bits are used as the simplest error detecting code.error detecting code As for binary digits, there are two variants of parity bits: even parity bit and odd parity bit: An even parity bit is set to 1 if the number of ones in a given set of bits is odd (making the total number of ones, including the parity bit, even). An odd parity bit is set to 1 if the number of ones in a given set of bits is even (making the total number of ones, including the parity bit, odd).

Examples: Ex1: Transmission sent using even parity: A transmits: 1001 A computes parity bit value: 1^0^0^1=0 (i.e. even number of ‘1’) A adds parity bit and sends:  error detecting code B receives: 1001 B computes parity: 1^0^0^1^0=0 (the same as the one computed by A) B reports correct transmission after observing expected even result. Ex2: transmission sent using odd parity: A transmits: 1001 A computes parity bit value: ~(1^0^0^1)=1 (i.e. even number of ‘1’) A adds parity bit and sends: B receives: B computes parity: 1^0^0^1^1=1 B reports correct transmission after observing expected odd result. Ex3: transmission sent using even parity: A transmits: 1001 A computes parity bit and sends: **** transmission error *** B receives: B computes parity: 1^1^0^1^0=1 (different from the one computed by A) B reports incorrect transmission after observing unexpected odd results ( cannot do the even number of corrupted bits, e.g.,  11011)

Test shift-right operator (shift right by 2 bits = divided by 2^2=4) (shift right by 3 bits = divided by 2^3=8) (shift right by 5 bits = divided by 2^5=32) P.S.: shift-left operator is for low active 3-8 decoder

∥ 4-bit 2-1 Multiplexer: 3-types (6 methods) 2-input and 1-output with 4-bit each

Vector sign extend Single-bit sign extend

Multi-bit concatenation (array) Single-bit concatenation

Shift right or left by 1 bit using concatenation operator ＝

1-bit half adder (unsigned) ∥ 1-bit full adder (unsigned)

∥ 4-bit ripple carry adder (unsigned) Method1: built-in adder Method2: Gate instan. using 1-bit full adder

Arithmetic operation rules: 1.option=ADD, result=a+b 2.option=SUB, result=a-b 3.option=AND, result= a&b 4.option=OR, result= a|b 5.option=XOR, result=a^b 6.default, result=a Arithmetic operation

Data-Flow Modelling-Operators Operator precedence: (see p.5-5 – 5-6) Logical and bit-wise NOT: !,~ Unary operators: &,~&,~|,^,~^ Arithmetic operators: +,-*,/,% Shift operators: > Relational operators:,>= Logic equality : ==,!=, Case operators: ===,!== Bitwise operators: &,~&,^,~^ Logical AND: && Logical OR: || Conditional operator: ?: high low