FLP data flow – FLP prototype Filippo Costa ALICE O 2 9 th June 2015 WUHAN, CHINA.

Slides:



Advertisements
Similar presentations
CWG10 Control, Configuration and Monitoring Status and plans for Control, Configuration and Monitoring 16 December 2014 ALICE O 2 Asian Workshop
Advertisements

Supported by GSI, BMBF (06FY9099I), EU (FP7-WP26) A Prototype Readout System for the MVD of the CBM Experiment Christoph Schrader for the CBM-MVD Collaboration.
LHCb Upgrade Overview ALICE, ATLAS, CMS & LHCb joint workshop on DAQ Château de Bossey 13 March 2013 Beat Jost / Cern.
Alice EMCAL Meeting, July 2nd EMCAL global trigger status: STU design progress Olivier BOURRION LPSC, Grenoble.
20 Feb 2002Readout electronics1 Status of the readout design Paul Dauncey Imperial College Outline: Basic concept Features of proposal VFE interface issues.
CHEP04 - Interlaken - Sep. 27th - Oct. 1st 2004T. M. Steinbeck for the Alice Collaboration1/20 New Experiences with the ALICE High Level Trigger Data Transport.
The Publisher-Subscriber Interface Timm Morten Steinbeck, KIP, University Heidelberg Timm Morten Steinbeck Technical Computer Science Kirchhoff Institute.
Quality Control B. von Haller 8th June 2015 CERN.
Hardware.  Learn what hardware is  Learn different input and output devices  Learn what the CPU is.
DDL hardware, DATE training1 Detector Data Link (DDL) DDL hardware Csaba SOOS.
Emulator System for OTMB Firmware Development for Post-LS1 and Beyond Aysen Tatarinov Texas A&M University US CMS Endcap Muon Collaboration Meeting October.
TRIGGER-LESS AND RECONFIGURABLE DATA ACQUISITION SYSTEM FOR POSITRON EMISSION TOMOGRAPHY Grzegorz Korcyl 2013.
GBT Interface Card for a Linux Computer Carson Teale 1.
Status of Data Exchange Implementation in ALICE David Evans LEADE 26 th March 2007.
ILC Trigger & DAQ Issues - 1 ILC DAQ issues ILC DAQ issues By P. Le Dû
MICE CM25 Nov 2009Jean-Sebastien GraulichSlide 1 Detector DAQ Issues o Achievements Since CM24 o Trigger o Event Building o Online Software o Front End.
The ALICE DAQ: Current Status and Future Challenges P. VANDE VYVRE CERN-EP/AID.
ALICE Upgrade for Run3: Computing HL-LHC Trigger, Online and Offline Computing Working Group Topical Workshop Sep 5 th 2014.
PACS IIDR 01/02 Mar 2001 On-Board Data Compression1 On-Board Data Compression Concept A. N. Belbachir Vienna University of Technology.
September 8-14, th Workshop on Electronics for LHC1 Channel Control ASIC for the CMS Hadron Calorimeter Front End Readout Module Ray Yarema, Alan.
A PCI Card for Readout in High Energy Physics Experiments Michele Floris 1,2, Gianluca Usai 1,2, Davide Marras 2, André David IEEE Nuclear Science.
Management of the LHCb DAQ Network Guoming Liu * †, Niko Neufeld * * CERN, Switzerland † University of Ferrara, Italy.
Next Generation Operating Systems Zeljko Susnjar, Cisco CTG June 2015.
Latest ideas in DAQ development for LHC B. Gorini - CERN 1.
News on GEM Readout with the SRS, DATE & AMORE
Guido Haefeli CHIPP Workshop on Detector R&D Geneva, June 2008 R&D at LPHE/EPFL: SiPM and DAQ electronics.
Front-End Electronics for PHENIX Time Expansion Chamber W.C. Chang Academia Sinica, Taipei 11529,Taiwan A. Franz, J. Fried, J. Gannon, J. Harder, A. Kandasamy,
CWG4 – The data model The group proposes a time frame - based data model to: – Formalize the access to data types produced by both detector FEE and data.
Pierre VANDE VYVRE for the O 2 project 15-Oct-2013 – CHEP – Amsterdam, Netherlands.
Predrag Buncic Future IT challenges for ALICE Technical Workshop November 6, 2015.
A Super-TFC for a Super-LHCb (II) 1. S-TFC on xTCA – Mapping TFC on Marseille hardware 2. ECS+TFC relay in FE Interface 3. Protocol and commands for FE/BE.
The Past... DDL in ALICE DAQ The DDL project ( )  Collaboration of CERN, Wigner RCP, and Cerntech Ltd.  The major Hungarian engineering contribution.
O 2 Project Roadmap P. VANDE VYVRE 1. O2 Project: What’s Next ? 2 O2 Plenary | 11 March 2015 | P. Vande Vyvre TDR close to its final state and its submission.
GBT-FPGA Interface Carson Teale. GBT New radiation tolerant ASIC for bidirectional 4.8 Gb/s optical links to replace current timing, trigger, and control.
A. KlugeFeb 18, 2015 CRU form factor discussion & HLT FPGA processor part II A.Kluge, Feb 18,
Management of the LHCb DAQ Network Guoming Liu *†, Niko Neufeld * * CERN, Switzerland † University of Ferrara, Italy.
Pierre VANDE VYVRE ALICE Online upgrade October 03, 2012 Offline Meeting, CERN.
CWG13: Ideas and discussion about the online part of the prototype P. Hristov, 11/04/2014.
Ken Wyllie, CERN Tracker ASIC, 5th July Overview of LHCb Upgrade Electronics Thanks for the invitation to Krakow!
PCIe40 — a Tell40 implementation on PCIexpress Beat Jost DAQ Mini Workshop 27 May 2013.
ECFA Workshop, Warsaw, June G. Eckerlin Data Acquisition for the ILD G. Eckerlin ILD Meeting ILC ECFA Workshop, Warsaw, June 11 th 2008 DAQ Concept.
Monitoring for the ALICE O 2 Project 11 February 2016.
ALICE O 2 project B. von Haller on behalf of the O 2 project CERN.
ALICE O 2 | 2015 | Pierre Vande Vyvre O 2 Project Pierre VANDE VYVRE.
Rutherford Appleton Laboratory September 1999Fifth Workshop on Electronics for LHC Presented by S. Quinton.
COMPASS DAQ Upgrade I.Konorov, A.Mann, S.Paul TU Munich M.Finger, V.Jary, T.Liska Technical University Prague April PANDA DAQ/FEE WS Игорь.
DHH at DESY Test Beam 2016 Igor Konorov TUM Physics Department E18 19-th DEPFET workshop May Kloster Seeon Overview: DHH system overview DHE/DHC.
The ALICE Data-Acquisition Read-out Receiver Card C. Soós et al. (for the ALICE collaboration) LECC September 2004, Boston.
Current STS Readout Concept 1 FEB 8 STS-XYTER Electrical Interface SLVS/LVDS pairs/FEB ROB GBTx / VL Optical Interface 4 MM fibers /ROB DPB.
Common Readout Unit (CRU) workshop CERN Mars 2016
Use of FPGA for dataflow Filippo Costa ALICE O2 CERN
Beam Wire Scanner (BWS) serial link requirements and architecture
DCH FEE STATUS Level 1 Triggered Data Flow FEE Implementation &
Workshop Concluding Remarks
Control of ASICs via GBTx
PANDA collaboration meeting FEE session
Continuous read-out: Triggers, Heart Beats, Timeframe
LHC experiments Requirements and Concepts ALICE
Electronics, Trigger and DAQ for SuperB
RT2003, Montreal Niko Neufeld, CERN-EP & Univ. de Lausanne
CRU Weekly Meeting Discussion on Trigger
ProtoDUNE SP DAQ assumptions, interfaces & constraints
PCI BASED READ-OUT RECEIVER CARD IN THE ALICE DAQ SYSTEM
Cover page.
Unit I Flash Cards Start.
TDAQ commissioning and status Stephen Hillier, on behalf of TDAQ
M. Krivda for the ALICE trigger project, University of Birmingham, UK
Sector Processor Status Report
TELL1 A common data acquisition board for LHCb
Juan Carlos Cabanillas Noris September 29th, 2018
Presentation transcript:

FLP data flow – FLP prototype Filippo Costa ALICE O 2 9 th June 2015 WUHAN, CHINA

Outline 2 Theory: –FLP data flow. Practice: –FLP prototype June, th Workshop on ALICE ITS, MFT and O2 | Wuhan, CHINA

3 Theory

4 June, th Workshop on ALICE ITS, MFT and O2 | Wuhan, CHINA Data flow FEE data FLP – EPN data flow

5 June, th Workshop on ALICE ITS, MFT and O2 | Wuhan, CHINA FLP data flow

6 June, th Workshop on ALICE ITS, MFT and O2 | Wuhan, CHINA Data are produced by the detectors in continuous or triggered read-out mode, synchronized by the trigger system. A mixture of readout links will be used: –DDL Gb/s –DDL2 max 6 Gb/s –GBT 3.2 / 3.52 / 4.48 Gb/s For the continuous detector the data stream is split into data frames using a reference trigger called heartBeat signal. The frames are accumulated over a period of 20 ms. FEE data flow

7 June, th Workshop on ALICE ITS, MFT and O2 | Wuhan, CHINA Several streams are aggregated and buffered in the memory of the FLP. These nodes perform a data reduction and compression of about 2.5 The FLPs produce a Sub-Time Frame (STF) that could be empty for the FLP receiving data from triggered detectors that didn’t receive triggers during that period of time FLP data flow

8 June, th Workshop on ALICE ITS, MFT and O2 | Wuhan, CHINA The STFs are then dispatched to the Event Processing Nodes (EPNs) for aggregation. All the STFs related to the same time period are sent to one EPN. The EPN communicates to the FLP its availability to receive data, so a proper load balanced list of EPNs can be prepared and used by the FLPs. FLP - EPN data flow

9 June, th Workshop on ALICE ITS, MFT and O2 | Wuhan, CHINA Time Frame

10 June, th Workshop on ALICE ITS, MFT and O2 | Wuhan, CHINA Time Frame

11 June, th Workshop on ALICE ITS, MFT and O2 | Wuhan, CHINA Time Frame The Data flow and processing will be based on the concept of Time Frame, all the data blocks will need to have a clear time identifiers

12 June, th Workshop on ALICE ITS, MFT and O2 | Wuhan, CHINA Time Frame descriptor The data granularity in Run3 is driven by the heartbeat (HB) signal, that is triggered at equal time intervals, on some bunch crossing ID. The time range is about 20 ms All the input data blocks acquired in a HB interval are assigned to a single Time Frame descriptor tag

13 June, th Workshop on ALICE ITS, MFT and O2 | Wuhan, CHINA Time Frame descriptor

14 June, th Workshop on ALICE ITS, MFT and O2 | Wuhan, CHINA FLP data aggregration

15 June, th Workshop on ALICE ITS, MFT and O2 | Wuhan, CHINA Practice

16 June, th Workshop on ALICE ITS, MFT and O2 | Wuhan, CHINA Schedule MILESTONE: –ITS half-layer test beginning 2017

17 June, th Workshop on ALICE ITS, MFT and O2 | Wuhan, CHINA FLP structure Infrastructure and services CCM Logging Logbook DQM …

18 June, th Workshop on ALICE ITS, MFT and O2 | Wuhan, CHINA FLP requirements Collect data from a card plugged in an FLP machine and output sub Time Frames to be used by data reduction processes via ALFA. Processes must be controlled centrally. Run conditions must be logged. Data must be monitored.

19 June, th Workshop on ALICE ITS, MFT and O2 | Wuhan, CHINA FLP software environment This section is covered by B. Von Haller –Tools and software process for the FLP prototype

20 June, th Workshop on ALICE ITS, MFT and O2 | Wuhan, CHINA FLP hardware environment

21 June, th Workshop on ALICE ITS, MFT and O2 | Wuhan, CHINA FLP prototype

22 June, th Workshop on ALICE ITS, MFT and O2 | Wuhan, CHINA 3 … 2 … 1 -> START

23 June, th Workshop on ALICE ITS, MFT and O2 | Wuhan, CHINA What do we have? Hardware: –FLP prototype –C-RORC (CRU style) –Plan B : AMC 40 board Software: –Everything listed before will be installed in the machine. Time: –Not a lot, but we already started working on the issue as much as we can. Coffee: –Plenty of it Brain: –Plugged in and working 100%

24 June, th Workshop on ALICE ITS, MFT and O2 | Wuhan, CHINA Thank you

25 June, th Workshop on ALICE ITS, MFT and O2 | Wuhan, CHINA References The GBT Project Home Page: The GBTx ASIC User Guide The GBT-FPGA Project Home Page The GBT_FPGA: one unified core for multiple users, ppt, M. Barros Marin, Feb The GBT_FPGA project, M. Barros Marin, S. Baron, ACES The GBT encoding scheme: “An Error-Correcting Line Coding ASIC for a HEP Rad-Hard Multi-GigaBit Optical Link”, G. Papotti, Proc. 2nd Conference on Ph.D. Research in Microelectronics and Electronics (PRIME 2006), Otranto (Lecce), Italy, June 2006, pp The GBT-FPGA Core: Features and Challenges, M. Barros Marin et al., 2015 JINST 7 P01075.

26 June, th Workshop on ALICE ITS, MFT and O2 | Wuhan, CHINA References ALICE DDL1/DDL2 protocol DDL, the ALICE Data Transmission Protocol and its Evolution from 2 to 6 Gb/s. Or Write an Filippo.costa at cern.ch

27 June, th Workshop on ALICE ITS, MFT and O2 | Wuhan, CHINA References ALICE DDL1/DDL2 protocol DDL, the ALICE Data Transmission Protocol and its Evolution from 2 to 6 Gb/s. Or Write an Filippo.costa at cern.ch