 Delay values control the time between the change in a right-hand-side operand and when the new value is assigned to the left- hand side.  Three ways.

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Presentation transcript:

 Delay values control the time between the change in a right-hand-side operand and when the new value is assigned to the left- hand side.  Three ways of specifying delays in continuous assignment statements are: ◦ regular assignment delay, ◦ implicit continuous assignment delay, and ◦ net declaration delay.

 The first method is to assign a delay value in a continuous assignment statement.  The delay value is specified after the keyword assign. Any change in values of in1 or in2 will result in a delay of 10 time units before recomputation of the expression in1 & in2, and the result will be assigned to out.  If in1 or in2 changes value again before 10 time units when the result propagates to out, the values of in1 and in2 at the time of recomputation are considered. This property is called inertial delay.  An input pulse that is shorter than the delay of the assignment statement does not propagate to the output.

The waveform in Figure on right is generated by simulating the above assign statement. It shows the delay on signal out. Note the following changes. 1. When signals in1 and in2 go high at time 20, out goes to a high 10 time units later (time = 30). 2. When in1 goes low at 60, out changes to low at However, in1 changes to high at 80, but it goes down to low before 10 time units have elapsed. 4. Hence, at the time of recomputation, 10 units after time 80, in1 is 0. Thus, out gets the value 0. A pulse of width less than the specified assignment delay is not propagated to the output.

 An equivalent method is to use an implicit continuous assignment to specify both a delay and an assignment on the net. //implicit continuous assignment delay wire #10 out = in1 & in2; //same as wire out; assign #10 out = in1 & in2;

 A delay can be specified on a net when it is declared without putting a continuous assignment on the net.  If a delay is specified on a net out, then any value change applied to the net out is delayed accordingly.  Net declaration delays can also be used in gate- level modeling. //Net Delays wire # 10 out; assign out = in1 & in2; //The above statement has the same effect as the following wire out; assign #10 out = in1 & in2;

 Example: `timescale 1ns/100ps module HalfAdder (A, B, Sum, Carry); input A, B; output Sum, Carry; assign #3 Sum = A ^ B; assign #6 Carry = A & B; endmodule 8

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