SOC Consortium Course Material ASIC Logic National Taiwan University Adopted from National Chiao-Tung University IP Core Design

SOC Consortium Course Material 2 Goal of This Lab  Prototyping  Familiarize with ARM Logic Module (LM)  Know how to program LM

SOC Consortium Course Material 3 Outline  Introduction  ARM System Overview  Prototyping with Logic Module  Lab – ASIC Logic

SOC Consortium Course Material 4 Introduction  Rapid Prototyping – A fast way to verify your prototype design. –Enables you to discover problems before tape out. –Helps to provide a better understanding of the design’s behavior.  ARM Integrator and Logic Module can be used for Hardware Design Verification and HW/SW co- verification. –Hardware Design Verification: using LM stand alone. –HW/SW co-verification: using LM, CM, Integrator together.

SOC Consortium Course Material 5 Outline  Introduction  ARM System Overview –ARM Synchronization Scheme: Interrupt –ARM Synchronization Scheme: Polling  Prototyping with Logic Module  Lab – ASIC Logic

SOC Consortium Course Material 6 ARM System Overview  A typical ARM system consists of an ARM core, a DSP chip for application-specific needs, some dedicated hardware accelerator IPs, storages, and some peripherals and controls.

SOC Consortium Course Material 7 ARM System Synchronization Scheme: Interrupt  A device asserts an interrupt signal to request the ARM core handle it.  The ARM core can perform tasks while the device is in use.  Needs Interrupt Controller. More hardware.

SOC Consortium Course Material 8 ARM System Synchronization Scheme: Polling  The ARM core keeps checking a register indicating if the device has done its task.  The ARM core is busy “polling” the device while the device is in use.  Less hardware.

SOC Consortium Course Material 9 Outline  Introduction  ARM System Overview  Prototyping with Logic Module –ARM Integrator AP & ARM LM –FPGA tools  Lab – ASIC Logic

SOC Consortium Course Material 10 AP Layout

SOC Consortium Course Material 11 What is LM  Logic Module  A platform for developing Advanced Microcontroller Bus Architecture (AMBA), Advanced System Bus (ASB), Advanced High- performance Bus (AHB), and Advanced Peripheral Bus (APB) peripherals for use with ARM cores.

SOC Consortium Course Material 12  It can be used in the following ways: –As a standalone system –With an CM, and a AP motherboard –As a CM with AP motherboard if a synthesized ARM core is programmed into the FPGA Using the LM

SOC Consortium Course Material 13 LM Architecture

SOC Consortium Course Material 14 Components of LM  Altera or Xilinx FPGA  Configuration PLD and flash memory for storing FPGA configurations  1MB ZBT SSRAM  Clock generators and reset sources  A 4-way flash image selection switch and an 8-way user definable switch  9 user-definable surface-mounted LEDs (8G1R)  User-definable push button  Prototyping grid  System bus connectors to a motherboard or other modules

SOC Consortium Course Material 15 LM Layout 8-way swtich 4-way swtich

SOC Consortium Course Material 16 Links  CONFIG link –Enable configuration mode, which changes the JTAG signal routing and is used to download new PLD or FPGA configurations.  JTAG, Trace, and logic analyzer connectors  Other links, switches, and small ICs can be added to the prototyping grid if required.

SOC Consortium Course Material 17 FPGA tools Xilinx GUI Synthesis Tool

SOC Consortium Course Material 18 On-board Clock Generators

SOC Consortium Course Material 19 Clock Signal Summary

SOC Consortium Course Material 20 Programming the LM Clock 1MHz:CTRLCLKx=19'b MHz:CTRLCLKx=19'b MHz:CTRLCLKx=19'b MHz:CTRLCLKx=19'b Constraint:

SOC Consortium Course Material 21 AHB Platform

SOC Consortium Course Material 22 Files Description  Hardware files. \Lab7\Codes\HW\example2\Verilog –AHBAHBTop.v –AHBDecoder.v –AHBMuxS2M.v –AHBZBTRAM.v –AHB2APB.v –AHBAPBSys.v –APBIntCon.v –APBRegs.v  Software program files. \Lab7\Codes\SW\example2\ –sw.mcp –logic.c –logic.h –platform.h –rw_support.s For Xilinx synthesis tool to generate lmxcv600e_72c_xcv2000e_via_reva_build0.bit For codewarrior to generate sw.axf

SOC Consortium Course Material 23 Software Description  5 files included in. \Lab7\Codes\SW\example2\ –sw.mcp: project file –logic.c: the main C code –logic.h: constant definitions –platform.h: constant definitions –rw_support.s: assembly functions for SSRAM testing

SOC Consortium Course Material 24 Integrator Memory Map

SOC Consortium Course Material 25 Work Flow Summary

SOC Consortium Course Material 26 Outline  Introduction  ARM System Overview  Prototyping with Logic Module  Lab – ASIC Logic

SOC Consortium Course Material 27 Reference [1] [1] LM-XCV2000E.pdf [2] DUI0098B_AP_UG.pdf [3] progcards.pdf

SOC Consortium Course Material 28 Experiment Requirements  Design an RGB-to-YUV converter that converts R, G, B values to Y, U, V values.  To implement the converter with pour software and write the test program.  To implement the converter into hardware and program it into the FPGA on the LM, evaluate the improvement compared to pure software implementation.