Orange Coast College Business Division Computer Science Department CS 116- Computer Architecture Peripherals

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 2 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Protocols An agreed-upon format for transmitting data between devices Can be implemented in HW or in SW Determines: – Type of error checking – Data compression method – How sending devices indicates “sending is finished” – How Receiving devices indicate “Received message”

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 3 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Protocols Ethernet: – LAN protocol – Also called CSMA/CD Carrier Sense Multiple Access with Collision Detection – Developed by Xerox – One of the simplest protocols – Uses bus or star topology – Widely implemented standard – Data transfer up to 10 Mbps

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 4 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Protocol Idea: – When devices has a message to transmit, it waits until the bus is idle then starts transmission – If the device detects distortion from other device that started transmission, both devices must stop transmission (Collision), then wait for a random time and then retransmit

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 5 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Protocols TCP/IP – Transmission Control Protocol/Internet Protocol – Suite of communication protocols – Connect hosts on the Internet – Capable of connecting different types of networks – Two main protocols: TCP & IP – The two protocols work together to form a “protocol stack”

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 6 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Protocols: TCP/IP IP: – Specifies the format of packets “Datagrams” and addressing scheme – Doesn’t guarantee reliable delivery TCP: – Establishes the connection between source and destination – Guarantees error-free delivery of messages

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 7 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Protocols Packet switching – Messages divided into packages before they are sent – Each packet is transmitted individually and can take different route from source to destination – Packets are recompiled at destination into original message – Used in sending and web-pages over the Internet

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 8 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Protocols: ATM Asynchronous Transfer Mode – Data transferred in packets (cells) of fixed size – Data transfer rate 155 Mbits/sec Gbit/sec – Creates a fixed channel (route) between two points – Transfer both voice & data

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 9 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Buses Bus – A collection of wires used to connect multiple subsystems – Transfers data & control signals – Internal bus: Connects internal computer components – Expansion bus: Enables expansion boards to connect to CPU & memory

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 10 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Buses Bus components: – Data bus Transfers actual data – Address bus Transfers information about where the data should go

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 11 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Buses Bus width – Size of the bus (in bits) – Determines how much data can be sent at one time Bus speed: – Number of bits sent across each wire each second Bridge: – Bus interface used to connect the buses and allow devices on one bus to talk to devices on another bus Memory Processor I/O Device

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 12 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Buses Peripheral Component Interconnect (PCI) Bus – Used for high performance devices – Local bus standard developed by Intel Industry Standard Architecture (ISA) Bus – Bus architecture used in IBM PC/AT AT-Bus – AT version of the ISA bus – Used for slower devices Plug & Play ISA – Enables the OS to configure expansion boards automatically – No need for changing dip-switches & jumpers

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 13 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Buses SCSI – Small Computer System Interface – An I/O bus (parallel interface standard) used for attaching peripheral devices to computers Used by Apple Macintosh computers PCs and many UNIX systems – Provide for faster data transmission Rates (up to 80 megabytes per second) – Can attach many devices to a single SCSI port

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 14 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Bus Example: Pentium Processor/ Memory Bus PCI Bus (Peripheral Component Interconnect ) I/O Busses

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 15 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Bus: Advantages Versatility: – New devices can be added easily – Peripherals can be moved between computer systems that use the same bus standard Low Cost: – A single set of wires is shared in multiple ways Modularity: – Manage complexity by partitioning the design

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 16 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Bus: Disadvantages Creates a communication bottleneck – The bandwidth of bus can limit the maximum I/O throughput Maximum bus speed (throughput) is limited by: – Length of the bus – Number of devices on the bus – Need to support a range of devices with: Widely varying latencies Widely varying data transfer rates

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 17 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Bus: General Organization Control lines: – Signal requests and acknowledgments (Bus protocol) – Indicate what type of information is on the data lines Data lines carry information between the source and the destination: – Data – Addresses – Complex commands Data & Address Lines Control Lines

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 18 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Bus Transaction Two parts: – Sending address – Sending/receiving data Defined by what they do to the memory – Read (output): Transfer data from memory to device – Write (input): Transfer data from device to memory Master/slave relationship: – One device (the master) controls one or more other devices (the slaves) Bus Master Bus Slave Master issues command Data can go either way

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 19 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Bus Transaction Bus Master: – Starts the bus transaction by issuing Command and address Bus Slave: – Responds to the address by: Sending data to the master if the master ask for data Receiving data from the master if the master wants to send data Send acknowledge signal indicating receiving command and/or finishing transaction A bus transaction includes two parts: – Request: Issuing the command (and address) – Action: Transferring (sending or receiving) the data

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 20 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Bus Transactions: Read / Output From memory to Device Steps a) Initiate a read from memory Control lines signal a read request to memory Data lines contain the address b) Memory accesses data c) Memory transfer data (output operation) over data bus Control line signal memory available Device stores data as it appears on the bus l l l

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 21 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Bus Transactions Read transaction: (memory  device/ processor] – Active participants are shown in (light brown) color – Right-side shaded => device is performing a read – Left-side shaded => device is performing a write Control lines Read request Data lines Disks a. b. c. Address Memory accessing data Data Data Ready Signal Memory Processor Control lines Data lines Disks

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 22 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Bus Transactions Write transaction – (Input) from device or processor into memory – Less time needed. Device doesn’t wait for memory access – Steps a) Control lines indicate write request Data lines contains address b) Memory is ready signal on control lines Data transferred on data lines Memory Control lines Data lines Disks a. b. Write request Address Memory ready Data Memory Processor Control lines Data lines Disks

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 23 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Types of Buses Terminology: – Backplane: A circuit board containing sockets into which other circuit boards can be plugged in An interconnection structure within the chassis – Active backplane Contains logic circuit that performs computing functions – Passive backplane Contains only sockets – Most PCs use active backplanes

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 24 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) A Picture

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 25 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Types of Buses a. One-Bus: – Processor-Memory Bus Backplane bus I/O devices ProcessorMemory P r oc esso r - mem o ry b us I/O bus Processor Bus adapter I/O bus Backplane bus P r oc esso r - mem o ry b us ProcessorMemory Bus adapter I/O bus c. Three buses Processor memory I/O bus Backplane bus b. Two-Buses: – Processor memory – I/O bus

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 26 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Types of Buses: One Bus System Processor-Memory Bus (IBM PC – AT) – Single bus used for both processor-memory & I/O devices-memory communication – Connects directly to the processor ProcessorMemory I/O Devices Backplane / Processor-Memory Bus

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 27 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Single Bus: Pros and Cons Advantages: – Simple – Low cost – Short – High speed (Optimized for cache block transfers) – Only need to match the memory system Maximize memory-to-processor bandwidth Disadvantages – Design specific – All devices connected to the bus must be known beforehand – Bus can become a major bottleneck

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 28 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Types of Buses: Two-Bus System I/O Bus (PCI & SCSI) – Tap into the processor-memory bus via bus adaptors (additional logic to interface between the bus & a device or between the backplane bus & the lower- level I/O bus) – Provide expansion slots for I/O devices – Processor-memory bus is mainly used for processor- memory traffic ProcessorMemory I/O Bus Processor Memory Bus Bus Adapter Bus Adapter Bus Adapter I/O Bus I/O Bus

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 29 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Two Bus: Pros and Cons Advantages: – Industry Standard – Used in different machines (standard) Disadvantages: – Lengthy – Slower – Need to match a wide range of I/O devices – Doesn’t directly interface with memory – Connects to either processor-memory or backplane bus to connect with memory

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 30 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Types of Buses: Three-Bus System Backplane Bus (SCSI) – A small number of backplane buses tap into the processor-memory bus – Processor-memory bus: Used for processor memory traffic – I/O buses: Connected to the backplane bus ProcessorMemory Processor Memory Bus Bus Adapter Bus Adapter I/O Bus Backplane Bus I/O Bus Bus Adapter

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 31 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Three Bus: Pros and Cons Advantages: – Industry standard / proprietary (owned) – Allow processors, memory, and I/O devices to coexist – Loading on the processor bus is greatly reduced – Less cost (one bus for all components) Disadvantages: – Must be designed to handle unknown devices with different latencies & bandwidth c/cs – Requires additional logic to interface

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 32 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Synchronous Bus Includes a clock in the control lines Fixed communication protocol that is relative to the clock Advantages: – Involves very little logic – Can run very fast Disadvantages: – Every device on the bus must run at the same clock rate – Should be short to avoid clock skews

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 33 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Asynchronous Bus Control lines serve to orchestrate sequencing Not clocked Advantages: – Accommodates a wide range of devices – Can be lengthened without worrying about clock skew Disadvantages: – Requires a “handshaking protocol” – Needs additional control line

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 34 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Bus Communication Protocols ° ° ° MasterSlave Control Lines Address Lines Data Lines Protocol: – Specification of sequence of events and timing requirements in transferring information Bus master controls the bus & initiates transaction Bus slave activated by the transaction

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 35 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Handshaking Protocol Uses 2 control signals; request & reply (ACK), to deal with timing of transfer Idea: – Each unit informs the other unit of its status – Error detected through time out mechanism Advantage: – Flexible – Reliable Other unit Slave Initiating unit Master Request Reply Data

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 36 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Bus Arbitration: Obtaining Access to the Bus How is the bus reserved by a devices that wishes to use it? – Arbitration The process of deciding which bus master gets to use the bus next One of the most important issues in bus design. Bus Master Bus Slave Control: Master initiates requests Data can go either way

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 37 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Bus Arbitration Chaos is avoided by a master-slave arrangement: – Only the bus master can control access to the bus: It initiates and controls all bus requests – A slave responds to read and write requests The simplest system: – Processor is the only bus master – All bus requests must be controlled by the processor – Disadvantage: The processor is involved in every transaction

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 38 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Bus Arbitration Bus Master responsibilities: – Assert the bus request – Cannot use the bus until its request is granted – Signal to the arbiter after finishing with using the bus Bus arbitration schemes balance two factors: – Bus priority: Highest priority device should be serviced first – Fairness: Avoids starvation Even the lowest priority device should never be completely locked out from the bus

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 39 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Bus Arbitration: Classes Daisy chain arbitration: – Uses priority scheme – Single device with all request lines. Centralized, parallel arbitration Distributed arbitration by self-selection: – Each device wanting the bus places a code indicating its identity on the bus. Distributed arbitration by collision detection: – Used by Ethernet

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 40 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Daisy Chain Bus Arbitration Scheme Highest priority device served first Advantage: Simple Disadvantages: – Cannot ensure fairness: A low-priority device may be locked out indefinitely – The use of the daisy chain grant signal limits the bus speed Bus Arbiter Device 1 Highest Priority Device N Lowest Priority Device 2 Grant Release Request wired-OR

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 41 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Centralized Parallel Arbitration Used in essentially all processor-memory busses and in high-speed I/O busses Bus Arbiter Device 1 Device N Device 2 Grant Req

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 42 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Bus Performance: Increase Bandwidth Use separate address and data lines: – Address and data can be transmitted in one bus cycle – Cost: More bus lines Increased complexity Increase data bus width: – Transfers of multiple words require fewer bus cycles – Cost: More bus lines

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 43 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Bus Performance: Increase Bandwidth Allow block (multiple-word) transfers: – Transfer multiple words in back-to-back bus cycles – Only one address needs to be sent at the beginning – The bus is not released until the last word is transferred – Cost: Increased complexity Decreased response time for request

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 44 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Bus Performance: Transaction Rate Assume a Multi-master bus Overlapped arbitration: – Perform arbitration for next transaction during current transaction Bus parking: – Master can hold onto bus and performs multiple transactions as long as no other master makes request Overlapped address / data phases: – Requires one of the above techniques

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 45 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Bus Performance: Transaction Rate Split-phase (or packet switched) bus: – Completely separate address and data phases – Arbitrate separately for each – Address phase yield a tag which is matched with data phase ”All of the above” in most modern memory busses

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 46 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Summary of Bus Options OptionHigh performanceLow cost Bus widthSeparate addressMultiplex address& data lines& data lines Data widthWider is fasterNarrower is cheaper (e.g., 32 bits)(e.g., 8 bits) Transfer sizeMultiple words hasSingle-word transferless bus overhead is simpler Bus mastersMultipleSingle master(requires arbitration)(no arbitration) ClockingSynchronousAsynchronous ProtocolPipelinedSerial