Instrumentation DepartmentJ. Coughlan et al.Rutherford Appleton Laboratory14 September 2000LEB2000 Krakow The Front-End Driver Card for CMS Silicon Microstrip Tracker Readout LEB2000 Krakow S.A.Baird, K.W.Bell, J.A.Coughlan, R.Halsall,W.J.Haynes, I.R.Tomalin CLRC Rutherford Appleton Laboratory E. Corrin Imperial College London Presented by John Coughlan

Instrumentation DepartmentJ. Coughlan et al.Rutherford Appleton Laboratory14 September 2000LEB2000 Krakow CMS Silicon Tracker Readout ~ 10 million Silicon Microstrips 80K APV25 readout chips ON Detector Analogue Optical readout 40K ADC readout system OFF Detector Level 1 rate ~ 100 kHz Front-End Driver: Optical receivers, ADCs, Digital processing, Buffering, DAQ interface Related talks... APV25 : Geoff Hall Optical Links : Francois Vasey LHC Test Beam : Nancy Marinelli Trigger Thottle System : Attila Racz Pixel Vertex Detector : Danek Kotlinski

Instrumentation DepartmentJ. Coughlan et al.Rutherford Appleton Laboratory14 September 2000LEB2000 Krakow FED Features Functions Optical Receiver ADC Digital Processing Cluster Finding Data Formatting DAQ Buffering Synchronisation Checking Local Monitoring Functions Optical Receiver ADC Digital Processing Cluster Finding Data Formatting DAQ Buffering Synchronisation Checking Local Monitoring Interfaces Front-End Electronics DAQ TTC Trigger Throttle & Synchronisation System Detector Controls System Interfaces Front-End Electronics DAQ TTC Trigger Throttle & Synchronisation System Detector Controls System

Instrumentation DepartmentJ. Coughlan et al.Rutherford Appleton Laboratory14 September 2000LEB2000 Krakow FED Architecture FPGA Opto Rx PD Array Prog Delay 1 Fibre ribbon 12 way Post ADC Processing TTCrx 1 FE 1 9 SBC DAQ SSRAM 2 2 fw X VME BSCAN FPGA 1 Dual ADC Dual ADC 1 6 FPGA Opto Rx PD Array 8 Post ADC Processing FE 8 8 Dual ADC Dual ADC Prog Delay Fibre ribbon 12 way READOUT ASIC DAQ Serial I/O RT Synch & Error Clock

Instrumentation DepartmentJ. Coughlan et al.Rutherford Appleton Laboratory14 September 2000LEB2000 Krakow Post ADC Processing Block ADC 1 10 trig1 sync 8 trig2 Ped sub 8 trig3 cm sub Re-order 10 8 Hit finding s-data s-addr8 16 hit Packetiser 8 8 headers token in data DPM 16 No hits Sequencer-mux 88 a d a d ADC trig1 sync 8 trig2 Ped sub 8 trig3 cm sub Re-order 10 8 Hit finding s-data s-addr8 16 hit Packetiser 8 token out data DPM 16 No hits Sequencer-mux 88 a d a d trig 8 headers averages

Instrumentation DepartmentJ. Coughlan et al.Rutherford Appleton Laboratory14 September 2000LEB2000 Krakow Backend Readout Block Data Merger 1 8 Prog Filter Format SSRAM INT INT DAQ INT Prog Filter Format TTC INT 9 SBC DAQ X VME FE FPGA 1 FE FPGA 8 SSRAM TTX Rx Ctrl FE FPGAs bus control etc VME FPGA 8 8 Trigger in Token back Token out

Instrumentation DepartmentJ. Coughlan et al.Rutherford Appleton Laboratory14 September 2000LEB2000 Krakow FED 9U Layout (96 ADC channels) Board Input rate 3 Gbyte/s Board Output Rate50 Mbyte/s per percent occupancy Board Input rate 3 Gbyte/s Board Output Rate50 Mbyte/s per percent occupancy

Instrumentation DepartmentJ. Coughlan et al.Rutherford Appleton Laboratory14 September 2000LEB2000 Krakow Final System 420 Boards96 ADC/Board 21 Crates 7 Racks 420 Boards96 ADC/Board 21 Crates 7 Racks 40 K ADC Channels10 Trigger Rate100 KHz Input Rate1.5 T Byte/s Output rate25 Gbyte/s/% 40 K ADC Channels10 Trigger Rate100 KHz Input Rate1.5 T Byte/s Output rate25 Gbyte/s/%

Instrumentation DepartmentJ. Coughlan et al.Rutherford Appleton Laboratory14 September 2000LEB2000 Krakow FED Modelling Basics Modelling as a tool Optimise the Design Optimising the cost performance ratio Elaborating & testing the Specification Modelling as a tool Optimise the Design Optimising the cost performance ratio Elaborating & testing the Specification Study Buffer Depths & Overflow Bus Speeds Algorithm Data Format Exception conditions & handling Data Flow control Different operating scenarios…. Study Buffer Depths & Overflow Bus Speeds Algorithm Data Format Exception conditions & handling Data Flow control Different operating scenarios…. Test Bench FED Model TTC - CLK... DAQ ‘VME’ ADC 0 ADC N Analyser Output Test Vectors DAQ Output Setup Param’s Monte Carlo Simulation Environment Digital HDL Simulator

Instrumentation DepartmentJ. Coughlan et al.Rutherford Appleton Laboratory14 September 2000LEB2000 Krakow FED Modelling Implementation Implementation 9U Design based on FED 1994 model Used in 1996 Beam Test 1 ADC Channel in ~25K Gate FPGA Limited at the time by FPGA technology Implementation 9U Design based on FED 1994 model Used in 1996 Beam Test 1 ADC Channel in ~25K Gate FPGA Limited at the time by FPGA technology Additional Features Re-ordering Pedestal Removal Threshold per strip Data range monitoring & limiting Sparsified & raw data readout Additional Features Re-ordering Pedestal Removal Threshold per strip Data range monitoring & limiting Sparsified & raw data readout adc 10 trig1 sync 8 trig2 Baseline (average) 8 trig3 Threshold (per strip) sdata saddr8 fifo 16 write 128 cycles ctr fifo 8No hits Packetiser 8 fifo 8proccessing status fifo 8 Raw Data token in token out data Quadrant data bus 8 trig2 Pedestal Removal Re-order

Instrumentation DepartmentJ. Coughlan et al.Rutherford Appleton Laboratory14 September 2000LEB2000 Krakow Software Architecture User Customisable within a RT framework Network VME Supervising WS CRATE SBCs Real Time OS Hardware FED, FEC, TTC FPGA USER Tracker System ‘Kernel’ GUI Network Tracker Crate ‘Kernel’ Memory Map Hardware Driver Network Calibration Setup Fast Monitoring Exception Handling Hit Finding Logic Analyser

Instrumentation DepartmentJ. Coughlan et al.Rutherford Appleton Laboratory14 September 2000LEB2000 Krakow FED Status & Plans Interfaces Status Opto Front-end specified (op-amp may be required) TTC Rx concept well defined Some areas less well defined, Throttle, Synchronisation (APV Emulation) DAQ Specification not fully defined - DAQ TDR Q4/2001 Modularity: FE-FED Mapping, Occupancy, DAQ Rates, load balancing Timescales PMC Prototype satisfies Labs and Test Beams Design & Modelling of Final FED until mid 2001 (Clustering algorithm ) Final FED Prototype for test beam 2002 Final FED Production start in 2003 Interfaces Status Opto Front-end specified (op-amp may be required) TTC Rx concept well defined Some areas less well defined, Throttle, Synchronisation (APV Emulation) DAQ Specification not fully defined - DAQ TDR Q4/2001 Modularity: FE-FED Mapping, Occupancy, DAQ Rates, load balancing Timescales PMC Prototype satisfies Labs and Test Beams Design & Modelling of Final FED until mid 2001 (Clustering algorithm ) Final FED Prototype for test beam 2002 Final FED Production start in 2003

Instrumentation DepartmentJ. Coughlan et al.Rutherford Appleton Laboratory14 September 2000LEB2000 Krakow FED-PMC Prototype 8 x 10 Bit 40 MHz ADC 64K Memory/per ADC 40 K Gate FPGA Control PCI Interface Mounts on Commercial VME CPU Board (or with an adapter in a PC slot) 30 in service 30 more about to be ordered Present Generation of ADC PMC Used in LHC test beam Y2000

Instrumentation DepartmentJ. Coughlan et al.Rutherford Appleton Laboratory14 September 2000LEB2000 Krakow 125 E-Net Switch FEC CRATES DCS Tracker Control WS TTC CRATES DAQ VME SBC RTOS Tracker Monitoring & Control Trigger Rate100 KHz Input Rate from FE1.5 T Byte/s Output rate to DAQ25 Gbyte/s per percent occupany D-BASE R/C 50K ADC Channels FED CRATES

Instrumentation DepartmentJ. Coughlan et al.Rutherford Appleton Laboratory14 September 2000LEB2000 Krakow Crate Layout LAN FE 1 DAQ TTC FE 2 FE 3 FE 4 FE 5 FE 6 FE 7 100MBit/s Crate Input Data Rate60 Gbyte/s Crate Output Data Rate1GByte/s per pecent occupancy B-Scan F-Bus NN Synch 100 KHz FE 8 Throttle