Project Goals 1.Get to know Quartus SoPC builder environment 2.Stream 2.Stream Video 3.Build 3.Build foundation for part B - Tracking system

Project Stages 1.Configure 1.Configure the system using SoPC builder 2.Create 2.Create embedded software 3.Generate 3.Generate system input using USB 4.Display 4.Display video

Costs DE2: 0/269/495$ (Academic/Commercial/) DE3: 0/?/2695$ Virtex 2 pro 299$(269/Ac/com) –Usb 2.0 ext. 39$

USB Basics

Host 1.Detect Attachment/Removal 2.Manage Control flow 3.Manage Data Flow Device 1.Respond to Requests Status Status Data Data

Isochronous Transfer 1.High priority 2.Low latency 3.No Resend on Error

System Architecture

Referenced Architecture 1.Tal Rath and Eyal Enav Configuration: Configuration:  NIOS II USB  Jungo configuration 2.DE2 demonstrations

Our Design Data flow inside the System Data flow inside the System Input from file Input from file Streaming format Streaming format

Video Streamer Packet Number Packet Data USB 38 Packets per frame

Packet Arrival

Interrupts NIOS II can be informed about a device finishing its process via IRQs. Devices we want the processor to have communication with, are assigned IRQs in the SOPC builder. Each IRQ is assigned a function in C, that will be called when an interrupt occurs.

Software

TIMELINE TIME

Why DMA? CPU can perform data transfers…CPU can perform data transfers… … but then it won’t be available for anything else… The DMA allows us to transfer data from one place to another without making use of the CPU.The DMA allows us to transfer data from one place to another without making use of the CPU.

Masters can operate concurrently if they don’t address the same slave. Masters in our design are the DMA’s and NIOS II architecture. Concurrent accesses to SDRAM happen when we write data from the USB to the SDRAM Avalon Bus

Direct Memory Access DMA receives:DMA receives: –Source –Destination –Amount of data to transfer

DMA USB INTERFACE USB DATA PORT PC sends a packet System receives INT DMA starts transfer System awaits next INT Transfer finishes

SRAM VGA INTERFACE

Access Collision

System with fifo Transmission done Reception done DMA streaming FIFO

Selected Design

Pixel Format Data Bytes per packet = 1022 Data Bytes per packet = 1022 Bytes per pixel = 2 Bytes per pixel = 2 Pixel per packet = 1022/2 = 511 Pixel per packet = 1022/2 = 511

24 vs 16 bit RGB 24 bit RGB16 bit RGB

Tools and Debug 1.Quartus II 1.Quartus II – Signal tap.Quartus II Quartus II 2.Model Sim 2.Model Sim – for design verificationModel Sim Model Sim 3.Logic analyser Logic analyserLogic analyser 4.Nios II IDE Nios II IDENios II IDE 5.Hex Editor Hex EditorHex Editor 6.Microsoft Visual Studio Microsoft Visual StudioMicrosoft Visual Studio

Troubleshooting 1.Quartus Quartus Version related issues USB Drivers 2.Model Sim Model SimModel Sim 3.Nios II IDE Nios II IDENios II IDE SoPC builder environment

VGA signals in Signaltap VGA signals in Signal tap

VGA signals in ModelSim

LogicAnalizer Logic Analizer Digital Scope Memory

Hex Editor Neo

Nios II IDE Memory view

Microsoft Visual studio 2005

Memory considerations 0.5 MB SRAM is not enough for possible extended image resolution (640x480). 8 MB of SDRAM will be enough for: 160x120x3x3 = 172,800 Bytes which is the current plan.

Summery StatusMilestone Done Learn SOPC environment (Quartus,Nios II IDE,SOPC builder ect.) Done Evaluate different VGA architectures Done Evaluate different DMA configurations Done Ramp up on USB 1.1 protocol Done Create interrupt driven software architecture Done Create internal protocol for streaming video Done Integration of different projects and platforms Done Evaluate alternative architectures for Steaming video system

2.Algorithm Motion image computation Mass center computation Prediction of next mass center (Kalman filter or more simple algorithm)