Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 11: October 1, 2010 Variation

Previously Understand how to model transistor behavior Given that we know its parameters –V dd, V th, t OX, C OX, W, L, N A … Penn ESE370 Fall DeHon 2 C GC C GCS C GCB

But… We don’t know its parameters (perfectly) 1.Fabrication parameters have error range 2.Identically drawn devices differ 3.Parameters change with environment 4.Parameters change with time Penn ESE370 Fall DeHon 3

Today Sources of Variation –Fabrication –Operation –Aging Coping with Variation –Margin –Corners –Binning Penn ESE370 Fall DeHon 4

Fabrication Penn ESE370 Fall DeHon 5

Process Shift Oxide thickness Doping level Layer alignment Growth and Etch times/rates Vary machine-to-machine, day-to-day Impact all transistors on wafer Penn ESE370 Fall DeHon 6

Region Correlated Parameters change consistently across wafer or chip based on location Chemical-Mechanical Polishing (CMP) –Dishing Lens distortion Penn ESE370 Fall DeHon 7

Penn ESE535 Spring DeHon 8 Oxide Thickness [Asenov et al. TRED 2002]

Penn ESE535 Spring DeHon 9 Line Edge Roughness 1.2  m and 2.4  m lines From:

Optical Sources What is the wavelength of light? How compare to 45nm feature size? Penn ESE370 Fall DeHon 10

Penn ESE535 Spring DeHon 11 Phase Shift Masking Source

Penn ESE535 Spring DeHon 12 Line Edges (PSM) Source:

Penn ESE535 Spring DeHon 13 Intel 65nm SRAM (PSM) Source:

Penn ESE535 Spring DeHon 14 Statistical Dopant Placement [Bernstein et al, IBM JRD 2006]

Random Trans-to-Trans Random dopant fluctuation Local oxide variation Line edge roughness Etch and growth rates Transistors differ from each other in random ways Penn ESE370 Fall DeHon 15

Penn ESE535 Spring DeHon 16 Source: Noel Menezes, Intel ISPD2007

Impact Changes parameters –W, L, t OX, V th Change transistor behavior Penn ESE370 Fall DeHon 17

Example: V th Many physical effects impact V th –Doping, dimensions, roughness Behavior highly dependent on V th Penn ESE370 Fall DeHon 18

Penn ESE535 Spring DeHon 19 V th 65nm [Bernstein et al, IBM JRD 2006]

Impact Performance V th  I ds  Delay (R on * C load ) Penn ESE370 Fall DeHon 20

Impact of V th Variation Penn ESE535 Spring DeHon 21

FPGA Logic Variation Altera Cyclone-II 90nm Penn ESE370 Fall DeHon 22 [Wong, FPT2007]

Operation Temperature Voltage Penn ESE370 Fall DeHon 23

Temperature Changes Different ambient environments –January in Maine –August in Philly –September in LA –Air conditioned machine room Self heat from activity of chip Quality of heat sink Penn ESE370 Fall DeHon 24

Voltage Power supply isn’t perfect Differs from design to design –Board to board? IR-drop in distribution Bounce with current spikes Penn ESE370 Fall DeHon 25

Aging Hot Carrier NBTI Penn ESE370 Fall DeHon 26

Hot Carriers Trap electrons in oxide –Also shifts V th Penn ESE370 Fall DeHon 27

NBTI Negative Bias Temperature Instability –Interface traps, Holes Long-term negative gate-source voltage –Affects PFET most Increase V th Partially recoverable? Temperature dependent Penn ESE370 Fall DeHon 28 [Stott, FPGA2010]

Measured Accelerated Aging Penn ESE370 Fall DeHon 29 [Stott, FPGA2010]

Coping with Variation Penn ESE370 Fall DeHon 30

Variation See a range of parameters –L: L min – L max –V th : V th,min – V th,max Penn ESE370 Fall DeHon 31

Penn ESE535 Spring DeHon 32 Variation Margin for expected variation Must assume V th can be any value in range –Speed  assume V th slowest value Probability Distribution V TH I on,min =I on (V th,max ) I d,sat  (V gs -V th ) 2

Variation See a range of parameters –L: L min – L max –V th : V th,min – V th,max Validate design at extremes –Work for both V th,min and V th,max ? –Design for worst-case scenario Penn ESE370 Fall DeHon 33

Margining Also margin for –Temperature –Voltage –Aging: end-of-life Penn ESE370 Fall DeHon 34

Process Corners Many effects independent Many parameters With N parameters, –Look only at extreme ends (low, high) –How many cases? Try to identify the {worst,best} set of parameters –Slow corner of design space, fast corner Use corners to bracket behavior Penn ESE370 Fall DeHon 35

Range of Behavior Still get range of performances Any way to exploit the fact some are faster? Penn ESE370 Fall DeHon 36 Probability Distribution Delay

Penn ESE535 Spring DeHon 37 Speed Binning Probability Distribution Delay Discard Sell Premium Sell nominal Sell cheap

Admin HW4 out today Andrew lecture on Monday –Explain how to understand pretty pictures on HW4 Andre out Tuesday Andre back for lecture on Wednesday Penn ESE370 Fall DeHon 38

Idea Parameters Approximate Differ –Chip-to-chip, transistor-to-transistor, over time Robust design accommodates –Tolerance and Margins Penn ESE370 Fall DeHon 39