Software and Hardware Support for Locality Aware High Performance Computing Xiaodong Zhang National Science Foundation College of William and Mary This talk does not necessarily reflect NSF`s official opinions

Acknowledgement l Participants of the project l David Bryan, Jefferson Labs (DOE) l Stefan Kubricht, Vsys Inc. l Song Jiang and Zhichun Zhu, William and Mary l Li Xiao, Michigan State University. l Yong Yan, HP Labs. l Zhao Zhang, Iowa State University. l Sponsors of the project l Air Force Office of Scientific Research l National Science Foundation l Sun Microsystems Inc.

CPU-DRAM Gap 60% per year 7% per year 50% per year

Cache Miss Penalty l A cache miss = Executing hundreds of CPU instructions (thousands in the future). l 2 GHz, 2.5 avg. issue rate: issue 350 instructions in 70 ns access latency. l A small cache miss rate  A high memory stall time in total execution time. l On average, 62% memory stall time for SPEC2000.

I/O Bottleneck is Much Worse l Disk access time is limited by mechanical delays. l A fast Seagate Cheetah X15 disk (15000 rpm): l average seek time: 3.9 ms, rotation latency: 2 ms l internal transfer time for a strip unit (8KB): 0.16 ms l Total disk latency: 6.06 ms. l External transfer rate increases 40% per year. l from disk to DRAM: 160 MBps (UltraSCSI I/O bus) l To get 8KB from disk to DRAM takes ms. l More than 22 million CPU cycles of 2GHz!

CPU Registers L1 TLB L3 L2 Row buffer DRAM Bus adapter Controller buffer Buffer cache CPU-memory bus I/O bus I/O controller disk Disk cache TLB registers L1 L2 L3 Controller buffer Buffer cache disk cache Row buffer Memory Hierarchy with Multi-level Caching Algorithm implementation Compiler Micro architecture Micro architecture Micro architecture Operating system

Other Systems Effects to Locality Locality exploitation is not guaranteed by the buffers! l Initial and runtime data placement. l static and dynamic data allocations, and interleaving. l Data replacement at different caching levels. l LRU is used but fails sometimes. l Locality aware memory access scheduling. l reorder access sequences to use cached data.

Outline u Cache optimization at the application level. l Designing fast and high associativity caches l Exploiting multiprocessor cache locality at runtime. u Exploiting locality in DRAM row buffer. l Fine-grain memory access scheduling. u Efficient replacement in buffer cache. l Conclusion

Application Software Effort: Algorithm Restructuring for Cache Optimization l Traditional algorithm design means: l to give a sequence of computing steps subject to minimize CPU operations. l It ignores: l inherent parallelizations and interactions (e.g. ILP, pipelining, and multiprogramming), l memory hierarchy where data are laid out, and l increasingly high data access cost.

Mutually Adaptive Between Algorithms and Architecture l Restructuring commonly used algorithms l by effectively utilizing caches and TLB, l minimizing cache and TLB misses. l A highly optimized application library is very useful. l Restructuring techniques l data blocking: grouping data in cache for repeat usage l data padding to avoid conflict misses l using registers as fast data buffers

Two Case Studies l Bit-Reversals: l basic operations in FFT and other applications l data layout and operations cause large conflict misses l Sortings: merge-, quick-, and insertion-. l TLB and cache misses are sensitive to the operations. l Our library outperforms systems approaches l We know exactly where to pad and block! l Usage of the two libraries (both are open sources) l bit-reversals: an alternative in Sun’s scientific library. l Sorting codes are used a benchmark for testing compilers.

Microarchitecture Effort: Exploit DRAM Row Buffer Locality l DRAM features: l High density and high capacity l Low cost but slow access (compared to SRAM) l Non-uniform access latency l Row-buffer serves as a fast cache l the access patterns here has been paid little attention. l Reusing buffer data minimizes the DRAM latency.

CPU Registers L1 TLB L3 L2 Row buffer DRAM Bus adapter Controller buffer Buffer cache CPU-memory bus I/O bus I/O controller disk Disk cache TLB registers L1 L2 L3 Controller buffer Buffer cache disk cache Row buffer Locality Exploitation in Row Buffer

DRAM Access = Latency + Bandwidth Time Precharge Row Access Bus bandwidth time DRAM Core Row Buffer Processor Column Access DRAMLatency

Nonuniform DRAM Access Latency l Case 1: Row buffer hit (20+ ns) l Case 2: Row buffer miss (core is precharged, 40+ ns ) l Case 3: Row buffer miss (not precharged, ≈ 70 ns) prechargerow accesscol. access row accesscol. access Row buffer misses come from a sequence of accesses to different pages in the same bank.

Amdahl’s Law applies in DRAM  As the bandwidth improves, DRAM latency will decide cache miss penalty.  Time (ns) to fetch a 128-byte cache block:

Row Buffer Locality Benefit Objective: serve memory requests without accessing the DRAM core as much as possible. Reduce latency by up to 67%.

Row Buffer Misses are Surprisingly High §Standard configuration l Conventional cache mapping l Page interleaving for DRAM memories l 32 DRAM banks, 2KB page size l SPEC95 and SPEC2000 §Why is the reason behind this?

Conventional Page Interleaving Page 0Page 1Page 2Page 3 Page 4Page 5Page 6Page 7 ………… Bank 0 Address format Bank 1Bank 2Bank 3 page indexpage offsetbank rpk

Address Mapping Symmetry cache tagcache set indexblock offset page indexpage offset tsb bank rpk cache-conflicting: same cache index, different tags. row-buffer conflicting: same bank index, different pages. address mapping: bank index  cache set index Property:  x  y, x and y conflict on cache  also on row buffer. page: cache:

Sources of Misses l Symmetry: invariance in results under transformations. l Address mapping symmetry propogates conflicts from cache address to memory address space: l cache-conflicting addresses are also row-buffer conflicting addresses l cache write-back address conflicts with the address of the to be fetched block in the row-buffer. l Cache conflict misses are also row-buffer conflict misses.

Breaking the Symmetry by Permutation-based Page Interleaving k XOR k page index page offset new bank k page offset indexbank L2 Cache tag

Permutation Property (1) §Conflicting addresses are distributed onto different banks memory banks Permutation-based interleaving L2 Conflicting addresses xor Different bank indexes Conventional interleaving Same bank index

Permutation Property (2) §The spatial locality of memory references is preserved. memory banks …… Within one page Permutation-based interleaving Conventional interleaving Same bank index xor Same bank index

Permutation Property (3) §Pages are uniformly mapped onto ALL memory banks. C+1P 2C+2P bank 0bank 1bank 2bank 3 C 2C+3P C+3P 2C 01P2P3P C+2P 2C+1P 4P5P6P7P ………… C+5PC+4PC+7PC+6P ………… 2C+6P2C+7P2C+4P2C+5P …………

Row-buffer Miss Rates

Comparison of Memory Stall Time

Improvement of IPC

Where to Break the Symmetry? l Break the symmetry at the bottom level (DRAM address) is most effective: l Far away from the critical path (little overhead) l Reduce the both address conflicts and write-back conflicts. l Our experiments confirm this (30% difference).

System Software Effort: Efficient Buffer Cache Replacement l Buffer cache borrows a variable space in DRAM. l Accessing I/O data in buffer cache is about a million times faster than in the disk. l Performance of data intensive applications relies on exploiting locality of buffer cache. l Buffer cache replacement is a key factor.

CPU Registers L1 TLB L3 L2 Row buffer DRAM Bus adapter Controller buffer Buffer cache CPU-memory bus I/O bus I/O controller disk Disk cache TLB registers L1 L2 L3 Controller buffer Buffer cache disk cache Row buffer Locality Exploitation in Buffer Cache

The Problem of LRU Replacement l File scanning: one-time accessed blocks are not replaced timely; l Loop-like accesses: blocks to be accessed soonest can be unfortunately replaced; l Accesses with distinct frequencies: Frequently accessed blocks can be unfortunately replaced. Inability to cope with weak access locality

Reasons for LRU to Fail and but Powerful Why LRU fails sometimes? A recently used block will not necessarily be used again or soon. The prediction is based on a single source information. Why it is so widely used? Simplicity: an easy and simple data structure. Work well for accesses following LRU assumption.

Our Objectives and Contributions Address the limits of LRU fundamentally. Retain the low overhead and strong locality merits of LRU. Significant efforts have been made to improve/replace LRU, Case by case; or High runtime overhead Our objectives:

Related Work l Aided by user-level hints l Application-hinted caching and prefetching [OSDI, SOSP,...] l rely on users` understanding of data access patterns. l Detection and adaptation of access regularities l SEQ, EELRU, DEAR, AFC, UBM [OSDI, SIGMETRICS …] l case-by-case oriented approaches l Tracing and utilizing deeper history information l LRFU, LRU-k, 2Q (VLDB, SIGMETRICS, SIGMOD …) l high implementation cost, and runtime overhead.

Observation of Data Flow in LRU Stack Blocks are ordered by recency in the LRU stack. Blocks enter the stack top, and leave from its bottom. A block evicted from the bottom of the stack should have been evicted much earlier ! LRU stack The stack is long and bottom is the only exit.

Inter-Reference Recency (IRR) IRR of a block: number of other unique blocks accessed between two consecutive references to the block. Recency: number of other unique blocks accessed from last reference to the current time IRR = 3 R = 2

Basic Ideas of LIRS l A high IRR block will not be frequently used. l High IRR blocks are selected for replacement. l Recency is used as a second reference. l LIRS: Low Inter-reference Recency Set algorithm l Keep Low IRR blocks in buffer cache. l Foundations of LIRS: l effectively use multiple sources of access information. l Responsively determine and change the status of each block. l Low cost implementations.

Data Structure: Keep LIR Blocks in Cache Low IRR (LIR) block and High IRR (HIR) block LIR block set (size is L lirs ) HIR block set Cache size L = L lirs + L hirs L hirs L lirs Physical Cache Block Sets

Replacement Operations of LIRS L lirs =2, L hirs =1 LIR block set = {A, B}, HIR block set = {C, D, E} E becomes a resident HIR determined by its low recency

D is referenced at time 10 The resident HIR block E is replaced ! Which Block is replaced ? Replace an HIR Block

How is LIR Set Updated ? LIR Block Recency is Used HIR is a natural place for D, but this is not insightful.

After D is Referenced at Time 10 D enters LIR set, and B steps down to HIR set Because D`s IRR< R max in LIR set

The Power of LIRS Replacement l File scanning: one-time access blocks will be replaced timely; (due to their high IRRs) l Loop-like accesses: blocks to be accessed soonest will NOT be replaced; (due to their low IRRs) l Accesses with distinct frequencies: Frequently accessed blocks will NOT be replaced. (dynamic status changes) Capability to cope with weak access locality

LIRS Efficiency: O(1) Rmax (Maximum Recency of LIR blocks) IRR HIR (New IRR of a HIR block) Yes!. this efficiency is achieved by our LIRS stack: Both recencies and useful IRRs are automatically recorded. Rmax of the block in the stack bottom is larger than IRRs of others. No comparison operations are needed. Can O(LIRS) = O(LRU)?

LIRS Operations resident in cache LIR block HIR block Cache size L = 5 L lir = 3 L hir = LIRS stack 5 3 LRU Stack for HIRs Initialization: All the referenced blocks are given an LIR status until LIR block set is full. We place resident HIR blocks in a small LRU Stack. Upon accessing an LIR block (a hit) Upon accessing a resident HIR block (a hit) Upon accessing a non-resident HIR block (a miss)

Access an LIR block (a Hit) S 5 3 Q S 5 3 Q Access 4Access 8 resident in cache LIR block HIR block Cache size L = 5 L lir = 3 L hir = S 5 3 Q 6 9 SdSd

Access an HIR Resident Block (a Hit) S 5 3 Q Access 3Access S 5 Q 5 resident in cache LIR block HIR block Cache size L = 5 L lir = 3 L hir = S 5 Q 5 2 SdSd

Access a Non-Resident HIR Block ( a Miss) Access S 7 Q S 5 Q 5 resident in cache LIR block HIR block Cache size L = 5 L lir = 3 L hir =2

Access a Non-Resident HIR block (a Miss) (Cont) resident in cache 5 block number LIR block HIR block Cache size L = 5 L lir = 3 L hir =2 Access S 7 Q S 9 Q Access 5 4 S Q

LIRS Stack Simplifies Replacement l Recency is ordered in stack with Rmax LIR block in bottom l No need to keep track of each HIR block`s IRR because l A newly accessed HIR block`s IRRs in stack = recency < R max. l A small LRU stack is used to store resident HIR blocks. l Additional operations of pruning and demoting are constant. l Although LIRS operations are much more dynamic than LRU, its complexity is identical to LRU.

Performance Evaluation l Trace-driven simulations on different patterns shows l LIRS outperforms existing replacement algorithms in almost all the cases. l The performance of LIRS is not sensitive to its only parameter L hirs. l Performance is not affected even when LIRS stack size is bounded. l The time/space overhead is as low as LRU. l LRU can be regarded as a special case of LIRS.

Selected Workload Traces 2-pools is a synthetic trace to simulate the distinct frequency case. cpp is a GNU C compiler pre-processor trace cs is an interactive C source program examination tool trace. glimpse is a text information retrieval utility trace. link is a UNIX link-editor trace. postgres is a trace of join queries among four relations in a relational database system sprite is from the Sprite network file system mulit1: by executing 2 workloads, cs and cpp, together. multi2: by executing 3 workloads, cs, cpp, and postgres, together. multi3: by executing 4 workloads, cpp, gnuplot, glimpse, and postgres, together (1) various patterns, (2) non-regular accesses, (3) large traces.

Looping Pattern: postgres (Time-space map)

Looping Pattern: postgres (Hit Rates)

Potential Impact of LIRS l A LIRS patent has been filed, pending for approval. l Has been positively evaluated by IBM Almaden Research. l A potential adoption from LaserFiche in digital library. l The trace-driven simulation package has been distributed to many universities for research and classroom teaching.

Conclusion Locality-aware research is long term and multidisciplinary. l Application software support l +: optimization is effective for architecture dependent library. l -: cache optimization only, and case by case l Hardware support l +: touching fundamental problems, such as address symmetry. l - : optimization space is very limited due to cost consideration. l System software support l +: a key for locality optimization of I/O and virtual memory l -: lack application knowledge, and kernel modifications.

Selected References l Application software for cache optimization l Cache effective sortings, ACM Journal on Exp. Alg., l Fast bit-reversals, SIAM Journal on Sci. Comp., 2001 l Fast and high associativity cache designs l Multicolumn caches, IEEE Micro, 1997 l Low power caches, IEEE Micro, l Hardware support for DRAM locality exploitation l Permutation-based page interleaving, Micro-33, l Fine-grain memory access scheduling, HPCA-8, l System software support buffer cache optimization l LIRS replacement, SIGMETRICS’02, l TPF systems, Software: Practice & Experience, 2002.