Technical University Tallinn, ESTONIA Component level dy Defect mapping Hierarchical Test Generation x1x1 x2x2 x3x3 x4x4 x5x5 System level WdWd Logic level Error Defect Hierarchical test (fault propagation) y* & & & 1 & & & Logic level Transistor level RT Level

Research in ATI © Raimund Ubar 2 1 Error 1  0 x 1 x 2 x 3 = 1 x 4 x 5 x 6 x 7 y F ( X ) SSBDD m l m l m,1 m 1 m 0 m T,1 m 0 l m,0 Root node Binary Decision Diagrams

Research in ATI © Raimund Ubar Generalization of BDDs m y 1 0 lmlm l1l1 l0l0 GyGy m Y h FkFk FnFn l0l0 l1l1 l2l2 lhlh lklk l k+1 F k+1 lnln lmlm GYGY Binary DD 2 terminal nodes and 2 edges from each node General case of DD n  2 terminal nodes and n  2 edges from each node Novelty: Boolean methods can be generalized in a straightforward way to higher functional levels 3

Technical University Tallinn, ESTONIA Faults and High-Level Decision Diagrams RTL-statement: Terminal nodes RTL-statement faults: data storage, data transfer, data manipulation faults Nonterminal nodes RTL-statement faults: label, timing condition, logical condition, register decoding, operation decoding, control faults K: ( If T,C) R D  F(R S1,R S2,…R Sm ),  N Testing concept on the DD-model (uniform for all nodes): 1) Exhaustive testing 2) Optimization

Technical University Tallinn, ESTONIA Test Generation for Digital Systems y 4 y 3 y 1 R 1 +R 2 IN+ R 2 R 1 *R 2 IN*R 2 y 2 R  0 R 2 IN R Multiple paths activation in a single DD Control function y 3 is tested Data path Decision Diagram High-level test generation with DDs: Conformity test Control: For D = 0,1,2,3: y 1 y 2 y 3 y 4 = 00D2 Data: Solution of R 1 + R 2  IN  R 1  R 1 * R 2 Test program:

Technical University Tallinn, ESTONIA Test Generation for Digital Systems High-level test generation with DDs: Conformity test Test template: Test program: For D = 0,1,2,3 Begin Load R1 = IN1 Load R2 = IN2 Apply IN = IN3 y 1 y 2 y 3 y 4 = 00D2 Read R2 End R2(D) Control: For D = 0,1,2,3: y 1 y 2 y 3 y 4 = 00D2 Data: Solution of R 1 + R 2  IN  R 1  R 1 * R 2

Technical University Tallinn, ESTONIA Test Generation for Digital Systems y 4 y 3 y 1 R 1 +R 2 IN+ R 2 R 1 *R 2 IN*R 2 y 2 R  0 R 2 IN R Single path activation in a single DD Data function R 1 * R 2 is tested Data path Decision Diagram High-level test generation with DDs: Scanning test Control: y 1 y 2 y 3 y 4 = 0032 Data: For all specified pairs of (R 1, R 2 ) Test program:

Technical University Tallinn, ESTONIA Test Generation for Digital Systems High-level test generation with DDs: Scanning test Control: y 1 y 2 y 3 y 4 = 0032 Data: For all specified pairs of (R 1, R 2 ) Test template: Test program: For j=1,n Begin Load R1 = IN(j 1 ) Load R2 = IN(j 2 ) y 1 y 2 y 3 y 4 = 0032: Read R2 End IN(j 1 ) IN(j 2 )R2(j) Test data Test results

Technical University Tallinn, ESTONIA Scan-Path for Making Systems Transparent Hierarhical test generation with Scan-Path: Bus Scan-Out

Technical University Tallinn, ESTONIA Testing with Minimal DFT for Scan-Path M 3 e + M 1 a * M 2 b   R 1 IN    c d y 1 y 2 y 3 y 4 Hierarhical test generation with Scan-Path: Control Part R 2 Bus Scan-In Scan-Out Data Part

Technical University Tallinn, ESTONIA Test Generation for Microprocessors I 1 :MVI A,DA  IN I 2 :MOV R,AR  A I 3 :MOV M,ROUT  R I 4 :MOV M,AOUT  IA I 5 :MOV R,MR  IN I 6 :MOV A,MA  IN I 7 :ADD RA  A + R I 8 :ORA RA  A  R I 9 :ANA RA  A  R I 10 :CMA A,DA   A Test program generation for a microprocessor (example): Instruction set: IR 3 A OUT 4 IA 2 R IN 5 R 1,3,4,6-10 IIN 1,6 A A 2,3,4,5 A + R 7 A  R 8 A  R 9  A 10 DD-model of the microprocessor:

Technical University Tallinn, ESTONIA Decision Diagrams for Microprocessors High-Level DD-based structure of the microprocessor (example): DD-model of the microprocessor: OUT R A IN I IR 3 A OUT 4 IA 2 R IN 5 R 1,3,4,6-10 IIN 1,6 A A 2,3,4,5 A + R 7 A  R 8 A  R 9  A 10 A + R

Technical University Tallinn, ESTONIA Test Program Synthesis for Microprocessors DD-model of the microprocessor: Scanning test program for adder: Instruction sequence T = I 5 (R)I 1 (A)I 7 I 4 for all needed pairs of (A,R) OUT I4I4 A I7I7 A R I1I1 IN(2) IN(1) R I5I5 Time: t t - 1 t - 2 t - 3 Observation Test Load IR 3 A OUT 4 IA 2 R IN 5 R 1,3,4,6-10 IIN 1,6 A A 2,3,4,5 A + R 7 A  R 8 A  R 9  A 10

Technical University Tallinn, ESTONIA Test Program Synthesis for Microprocessors Scanning test program for adder: Instruction sequence T = I 5 (R)I 1 (A)I 7 I 4 for all needed pairs of (A,R) OUT I4I4 A I7I7 A R I1I1 IN(2) IN(1) R I5I5 Time: t t - 1 t - 2 t - 3 Observation Test Load Test program: For j=1,n Begin I 5 : Load R = IN(j 1 ) I 1 : Load A = IN(j 2 ) I 7 : ADD A = A + R I 4 : Read A End IN(j 1 ) IN(j 2 )A Test data Test results

Technical University Tallinn, ESTONIA Test Program Synthesis for Microprocessors DD-model of the microprocessor: Conformity test program for decoding I: Instruction sequence T = I 5 I 1 D I 4 for all D  I 1 - I 10  at given A,R,IN(3) OUT I4I4 A I = I D A R I1I1 IN(2) IN(1) R I5I5 Time: t t - 1 t - 2 t - 3 Observation Test Load IR 3 A OUT 4 IA 2 R IN 5 R 1,3,4,6-10 A I IN 1,6 A 2,3,4,5 A + R 7 A  R 8 A  R 9  A 10 IN(3)

Technical University Tallinn, ESTONIA Test Program Synthesis for Microprocessors Conformity test program for decoding I: Instruction sequence T = I 5 I 1 D I 4 for all D  I 1 - I 10  at given A,R,IN(3) OUT I4I4 A I = I D A R I1I1 IN(2) IN(1) R I5I5 Time: t t - 1 t - 2 t - 3 Observation Test Load IN(3) Test program: For j=1,n Begin I 5 : Load R = IN(1) I 1 : Load A = IN(2) I D : D I 4 : Read A End IjIj A Test data Test results

Technical University Tallinn, ESTONIA Test Data for Microrocessors Conformity test program for I in A: Instruction sequence T = I 5 I 1 D I 4 for all D  I 1 - I 10  at given A,R,IN Data IN,A,R are generated so that the values of all functions were different Response: RRR Test: D Test data generation: IN  A  ( A+R)  (A  R)  ( A  R)   A Find IN, A, R by solving the inequality: A I IN 1,6 A 2,3,4,5 A + R 7 A  R 8 A  R 9  A 10

Technical University Tallinn, ESTONIA Test Data for Microrocessors Conformity test program for decoder: Instruction sequence T = I 5 I 1 D I 4 for all D  I 1 - I 10  at given A,R,IN Data generation: Data IN,A,R are generated so that the values of all functions were different Final test program: StepIModeINAR 1I5I5 Load R110 2I1I1 Load A IDID Test I4I4 ObserveRRR Response: RRR Test: D IN  A  ( A+R)  (A  R)  ( A  R)   A Find IN, A, R by solving the inequality:

Research in ATI © Raimund Ubar 19 OPBSemanticRT level operations 0 0READ memoryR(A1) = M(A)PC = PC + 2 1WRITE memoryM(A) = R(A2)PC = PC TransferR(A1) = R(A2)PC = PC + 1 1Complement R(A1) =  R(A2) PC = PC AdditionR(A1) = R(A1)+ R(A2)PC = PC + 1 1SubtractionR(A1) = R(A1)- R(A2)PC = PC JumpPC = A 1Conditional jumpIF C=1, THEN PC = A,ELSE PC = PC + 2 From MP Instruction Set to RTL Structure OP B 0 M(A) 1 R(A2) M(A) OP 0 PC 1, 2 B 3 A 0 PC + 2 PC + 1 C A1 R0R0 0 R(A1) R1R1 1 R2R2 2 R3R3 3 A2 R0R0 0 R(A2) R1R1 1 R2R2 2 R3R3 3 A1 = 0 R0R0 R0R0 0 1 A1 = 3 R3R3 R3R3 0 1 R 1, R 2 OP B0B0 0 M(A) 1 0 B1B1 1 R(A2) 1 0 B2B R(A1) - R(A2) 3 R(A1) R(A1) + R(A2) R(A1) Instruction code: ADD A1 A2 OP=2. B=0. A1=3. A2=2 R 3 = R 3 + R 2 PC = PC+1

Research in ATI © Raimund Ubar 20 HLDDs for MP InstrSet A1 = 0 R0R0 R0R0 0 OP B0B0 1 0 M(A) 1 0 B1B1 1 R(A2) 1 0 B2B R(A1) - R(A2) 3 A1 = 3 R3R3 R3R3 0 1 R 1, R 2 R(A1) R(A1) + R(A2) R(A1) Registers and ALU A1 R0R0 0 R(A1) R1R1 1 R2R2 2 R3R3 3 A2 R0R0 0 R(A2) R1R1 1 R2R2 2 R3R3 3 Register Decoding OP 0 PC 1, 2 B 3 A 0 PC + 2 PC + 1 C Program Counter OP B 0 M(A) 1 R(A2) M(A) Memory Access Instruction code: ADD A1 A2 OP=2. B=0. A1=3. A2=2 R 3 = R 3 + R 2 PC = PC+1

Research in ATI © Raimund Ubar 21 Scanning Test Algorithm Test Algorithm for the terminal node m in HLDD G z FOR t = 1,2, …, p Initialize the data registers R(m) with R(m,t) Execute the working mode under test READ the result. END. The number p depends on how many operands is needed for testing the function of the terminal node A1 = 0 R0R0 R0R0 0 1 A1 = 3 R3R3 R3R3 0 1 R 1, R 2 OP B0B0 0 M(A) 1 0 B1B1 1 R(A2) 1 0 B2B R(A1) - R(A2) 3 R(A1) R(A1) + R(A2) R(A1) Terminal node m Data registers R(A1), R(A2) to be initialized Data register R 3 to be read

Research in ATI © Raimund Ubar 22 Example: Scanning Test Program OP B 0 M(A) 1 R(A2) M(A) OP 0 PC 1, 2 B 3 A 0 PC + 2 PC + 1 C A1 R0R0 0 R(A1) R1R1 1 R2R2 2 R3R3 3 A2 R0R0 0 R(A2) R1R1 1 R2R2 2 R3R3 3 A1 = 0 R0R0 R0R0 0 1 A1 = 3 R3R3 R3R3 0 1 R 1, R 2 OP B0B0 0 M(A) 1 0 B1B1 1 R(A2) 1 0 B2B R(A1) - R(A2) 3 R(A1) R(A1) + R(A2) R(A1) FOR t =0,1,2, …, n LDA 2, A(0+t) (Initialize R2 = R2(t)) LDA 3, A(10+t) (Initialize R3 = R3(t)) ADD 3, 2 (Execute the instruction OP.B.A1.A2 = ) STA A(20+t),2 (Write the content of R3 into M(20+t)) END FOR

Research in ATI © Raimund Ubar 23 Conformity Test Algorithm Test algorithm for testing the nonterminal node m in HLDD G z (Testing the node variable z(m) exhaustively for all its values): FOR all v  V(z(m)) FOR t = 1,2, …, p Initialize the data registers R(m) with contents R(m,t) Execute the working mode under test READ the value of z (HLDD functional variable). END FOR The number p 1 depends on how many operands is needed to satisfy the constraints of the fault model A1 = 0 R0R0 R0R0 0 1 A1 = 3 R3R3 R3R3 0 1 R 1, R 2 OP B0B0 0 M(A) 1 0 B1B1 1 R(A2) 1 0 B2B R(A1) - R(A2) 3 R(A1) R(A1) + R(A2) R(A1)

Research in ATI © Raimund Ubar 24 Example: Conformity Test Program OP B 0 M(A) 1 R(A2) M(A) OP 0 PC 1, 2 B 3 A 0 PC + 2 PC + 1 C A1 R0R0 0 R(A1) R1R1 1 R2R2 2 R3R3 3 A2 R0R0 0 R(A2) R1R1 1 R2R2 2 R3R3 3 A1 = 0 R0R0 R0R0 0 1 A1 = 3 R3R3 R3R3 0 1 R 1, R 2 OP B0B0 0 M(A) 1 0 B1B1 1 R(A2) 1 0 B2B R(A1) - R(A2) 3 R(A1) R(A1) + R(A2) R(A1) FOR VAR=0,1,2,3 LDA 2, 1 (Initialize R2 = M(1)) LDA 3, 2(Initialize R3 = M(2)) Execute: I = VAR.0.3.2(Testing of instructions: LDA, MOV, ADD, JMP) STA 3, 10+VAR (Write the content of R3 into M(10+VAR)) END FOR Data must satisfy the constraints: M(A)  R2  (R2 + R3)  R3

Research in ATI © Raimund Ubar 25 Fault Activating in Microprocessors For testing a node, three actions are needed: -Local fault activating at a node by satisfying the constraints -Topologigal propagation of the fault through the HLDD -System level propagation of a fault through the system of HLDDs  i,j  V(z(m)) [z(m i )  (z(m j )] Constraints for testing the node m New fault model: m R m 1 m v* m 0 m k k m n n V* 1

Research in ATI © Raimund Ubar State of Art: Microprocessor Fault Model Source decoding (MUX): F1: no source is selected F2: wrong source is selected; F3: more than one source is selected and the multiplexer output is either a wired-AND or a wired-OR function of the sources, depending on the technology. Destination decoding (DMUX) F4: no destination is selected F5: instead of, or in addition to the selected correct destination, one or more other destinations selected Instruction exec. faults F6: one or more microorders not activated F7: microorders are erroneously activated F8: a different set of micro instructions is activated instead of, or in addition to Data storage/bus/ALU faults: F9: one or more cells SAF0 /1; F10: one or more cells fail 0  1/1  0 F11: two or more cells coupled; F12: one or more lines SAF0 /1; F13:one or more lines wired-OR/AND F14: data manipulation faults Thatte’1980

Research in ATI © Raimund Ubar 27 Fault Modeling in Microprocessors

Research in ATI © Raimund Ubar 28 Fault Modeling in Microprocessors

Research in ATI © Raimund Ubar Hard-to-Test Faults in Microprocessors Instruction set: I 0 : C = AB I 1 : C =  (AB) I 2 : D = A v B I 3 : D =  (A v B) OR-type of short between the outputs 1 and 2 of decoder i.e. The instruction I 1 implys additionally I 2. Normally, when testing I 1, we read only the register C, but we do not read the register D I AB 0 C  AB 1 C 2, 3 I ABAB 2D ABAB 3 D 0,1 New fault type: Added not intended functionality DC & & 1 & 1 & & 1 I A B C D Fault

Research in ATI © Raimund Ubar 30 Instruction set: I 1 : Load R 1 and R 2 with D I 2 : Read R 1 I 3 : Read R 2 Fault Masking in Microprocessors

Research in ATI © Raimund Ubar 31 Instruction Based Test with Fault Masking Memory R1R1 R2R2 I1I1 F2: Fault during Load by I 1 I2I2 F1: Faulty Load by I 2 I3I3 Instruction set: I 1 : Load R 1 and R 2 with D I 2 : Read R 1 I 3 : Read R 2 I1I1 Testing the instruction I 1 : I 1 : R 1 = D, R 2 =D* (D* is a faulty value) I 2 : Read R 1 (correct reading), but R 2 = D (the faulty value D* is overwritten with the correct value of D) I 3 : Read R 2 (correct reading, the fault F2 was escaped).

Research in ATI © Raimund Ubar Avoidance of Fault Masking Memory R1R1 R2R2 I1I1 F2: Fault during Load by I 1 I2I2 F1: Faulty Load by I 2 I3I3 Instruction set: I 1 : Load R 1 and R 2 with D I 2 : Read R 1 I 3 : Read R 2 I1I1 In the proposed approach, instead of testing the instruction, we test the the functional variables R 1 and R 2 separately: Testing R 1 : I 1 : R 1 =D, R 2 =D* (D* is the faulty value) I 2 : Read R 1 = D (correct reading) Testing R 2 : I 1 : R 1 =D, R 2 =D* (D* is the faulty value) I 3 : Read R 2 = D* (the fault is detected)

Research in ATI © Raimund Ubar Diagnostic Capability of the Test Memory R1R1 R2R2 I1I1 F2: Fault during Load by I 1 I2I2 F1: Faulty Load by I 2 I3I3 Instruction set: I 1 : Load R 1 and R 2 with D I 2 : Read R 1 I 3 : Read R 2 I1I1 Test Fault table ResultComments TIF1F2 T1T1 I1I2I3I1I2I3 110 Testing the behavior of R2 during I 2 F2 is masked by F1 T2T2 I1I3I1I3 011 F2 is detected F1 still not detected I M 1 R2 R2R2 2,3 I M 1 M R1R1 2 R2R2 3

Research in ATI © Raimund Ubar Improving Diagnostic Resolution Memory R1R1 R2R2 I1I1 F2: Fault during Load by I 1 I2I2 F1: Faulty Load by I 2 I3I3 Instruction set: I 1 : Load R 1 and R 2 with D I 2 : Read R 1 I 3 : Read R 2 I 4 : Load R 2 (New added instruction) I1I1 Test Fault table ResultComments TIF1F2 T1T1 I1I3I1I3 011Detected fault T2T2 I1I2I3I1I2I3 110 Masking of a fault F2 is suspected, F1 may be as well the case T3T3 I1I4I3I1I4I3 010 Overwritten fault No suspiction about F1 I M 1 R2 R2R2 2,3 M 4 I M 1,4 M R1R1 2 R2R2 3

Research in ATI © Raimund Ubar 35 Method and its Side Effects Side effects: 1)Special type of test compaction: DD model Test program template ATPG 2)When testing all the functions of A with the same LOAD and READ conditions, the probability of fault masking will reduce 3)The faults of type “added erroneous actions” are as well easily tested Given: A system of HLDDs A set TT of test templates (subprograms) Mapping of HLDD nodes into TT Algorithm: For each HLD For each node m Activate all the paths to and from m Calculate the set of needed states of MP Insert the calculation results into the template END Test program: For each HLDm For each node m Carry out the test template TT(m) END

Research in ATI © Raimund Ubar MUXWRITEREADALUDMUX y1y1 TransferA1A1 AddressingA2A2 y2y2 Operationy3y3 Transfer 0M1=ALU0R 0 = M10M2 = R 0 0ALU = A0OUT = M2 1M1 = IN1R 1 = M11M2 = R 1 1 ALU= B 1B = M2  2R 2 = M12M2 = R 2 2ALU=A + B2A = M2  3ALU= A - B  RISC-Processor DMUX1 y 3 DMUX ALU A 1 R 0 R 1 R 2 R 0 R 1 R 2 R B MUX y 1 y ROUT A 2 y 2 M1 RIN M2 A

0 M1M1 R0R0 A1A1 R0R0 R1R1 A1A1 R0R0 R2R2 A1A1 R0R0 1 2 M1M1 y1y1 0 IN 0 y2y2 A B A+B 1 2 A-B OUT y3y3 A2A2 R0R0 B y3y3 B R1R1 R1R A y3y3 2 RISC Processor and its HLDD model Register block Output behaviour ALU

0 M1M1 R0R0 A1A1 R0R0 R1R1 A1A1 R0R0 R2R2 A1A1 R0R0 1 2 M1M1 y1y1 0 IN 0 y2y2 A B A+B 1 2 A-B OUT y3y3 A2A2 R0R0 B y3y3 B R1R1 R1R A y3y3 2 0 y3y3 A2A2 R0R0 y3y3 B R1R1 R2R M1M1 A1A1 A1A1 A1A1 1 2 y1y1 0 IN 0 y2y2 A B A+B 1 2 A-B 3 1 A y3y3 2 RISC Processor and its HLDD model Network level model System level model

0 OUT y3y3 A2A2 R0R0 y3y3 B R1R1 R2R M1M1 A1A1 A1A1 A1A1 1 2 y1y1 0 IN 0 y2y2 A B A+B 1 2 A-B 3 1 A y3y3 2 0 OUT y3y3 A2A2 R0R0 y3y3 B R1R1 R2R M1M1 A1A1 A1A1 A1A1 1 2 y1y1 0 IN 0 y2y2 A B A+B 1 2 A-B 3 1 A y3y3 2 Ty1y1 y2y2 y3y3 A1A1 A2A2 INR0R0 R1R1 R2R2 BAOUT 110D1 Ty1y1 y2y2 y3y3 A1A1 A2A2 INR0R0 R1R1 R2R2 BAOUT D1 Test Program Generation: Test 1 Test step 1: Load R 0 Test step 2: Testing ALU (M1 = A, Transfer A to R 1 )

0 OUT y3y3 A2A2 R0R0 y3y3 B R1R1 R2R M1M1 A1A1 A1A1 A1A1 1 2 y1y1 0 IN 0 y2y2 A B A+B 1 2 A-B 3 1 A y3y3 2 0 OUT y3y3 A2A2 R0R0 y3y3 B R1R1 R2R M1M1 A1A1 A1A1 A1A1 1 2 y1y1 0 IN 0 y2y2 A B A+B 1 2 A-B 3 1 A y3y3 2 Ty1y1 y2y2 y3y3 A1A1 A2A2 INR0R0 R1R1 R2R2 BAOUT 31021D2D1 D2D1 Ty1y1 y2y2 y3y3 A1A1 A2A2 INR0R0 R1R1 R2R2 BAOUT 41102D3 D1D2 Test step 3: Read R 1 Load R 2 Test Program Generation: Test 1/2 Test Program Generation: Test 2 Test step 4: Load B, Load R 0

0 OUT y3y3 A2A2 R0R0 y3y3 B R1R1 R2R M1M1 A1A1 A1A1 A1A1 1 2 y1y1 0 IN 0 y2y2 A B A+B 1 2 A-B 3 1 A y3y3 2 0 OUT y3y3 A2A2 R0R0 y3y3 B R1R1 R2R M1M1 A1A1 A1A1 A1A1 1 2 y1y1 0 IN 0 y2y2 A B A+B 1 2 A-B 3 1 A y3y3 2 Ty1y1 y2y2 y3y3 A1A1 A2A2 INR0R0 R1R1 R2R2 BAOUT D3D2 Ty1y1 y2y2 y3y3 A1A1 A2A2 INR0R0 R1R1 R2R2 BAOUT D5D2 Test Program Generation: Test 2 Test step 5: Testing ALU (M1 =  B), Transfer M1 to R 1, Read R 1 Test 3 Test step 6: Testing ALU (M1 = A+B), Transfer M1 to R 0

0 OUT y3y3 A2A2 R0R0 y3y3 B R1R1 R2R M1M1 A1A1 A1A1 A1A1 1 2 y1y1 0 IN 0 y2y2 A B A+B 1 2 A-B 3 1 A y3y3 2 0 OUT y3y3 A2A2 R0R0 y3y3 B R1R1 R2R M1M1 A1A1 A1A1 A1A1 1 2 y1y1 0 IN 0 y2y2 A B A+B 1 2 A-B 3 1 A y3y3 2 Ty1y1 y2y2 y3y3 A1A1 A2A2 INR0R0 R1R1 R2R2 BAOUT 71010D4D5D4D2 D5 Ty1y1 y2y2 y3y3 A1A1 A2A2 INR0R0 R1R1 R2R2 BAOUT D5D4D6D2D4 902D6 Test Program Generation: Test 2/3 Test step 7: Read R 0 Load R 1 Test step 8: Testing ALU (M1 = A-B), Transfer M1 to R 2 Test step 9: Read R 02 Test 4

Test step Control partData part y1y1 y2y2 y3y3 A1A1 A2A2 INR0R0 R1R1 R2R2 BA OUT 110D D2 D D3 D D5D D4 D D6D4 902D6 Fault cove- rage 2/24/43/ Full Test Program and High Level Fault Table

0 M1M1 A1A1 A1A1 A1A1 1 2 y1y1 0 IN 0 y2y2 A B A+B 1 2 A-B OUT y3y3 A2A2 R0R0 y3y3 B R1R1 R2R A y3y3 2 0 y3y3 A2A2 R0R0 y3y3 B R1R1 R2R A y3y3 2 Ty1y1 y2y2 y3y3 A1A1 A2A2 INR0R0 R1R1 R2R2 BAOUT 31021D2D1 D2D1 Generation of Diagnostic Tree Backtracing of test step 3

OUT B 0 M1M1 A1A1 A1A1 A1A1 1 2 y1y1 0 IN 0 y2y2 A B A+B 1 2 A-B 3 1 A 0 y3y3 A2A2 R0R0 y3y3 R1R1 R2R y3y3 2 0 OUT y3y3 A2A2 R0R0 y3y3 B R1R1 R2R A y3y3 2 0 M1M1 A1A1 A1A1 A1A1 1 2 y1y1 0 IN 0 y2y2 A B A+B 1 2 A-B 3 1 Ty1y1 y2y2 y3y3 A1A1 A2A2 INR0R0 R1R1 R2R2 BAOUT D1 0 y3y3 A2A2 R0R0 y3y3 R1R1 R2R y3y3 2 Generation of Diagnostic Tree Backtracing of test step 2

0 OUT y3y3 A2A2 R0R0 y3y3 B R1R1 R2R A y3y3 2 0 M1M1 A1A1 A1A1 A1A1 1 2 y1y1 0 IN 0 y2y2 A B A+B 1 2 A-B y3y3 A2A2 R0R0 y3y3 R1R1 R2R y3y3 2 0 M1M1 A1A1 A1A1 A1A1 1 2 y1y1 0 IN 0 y2y2 A B A+B 1 2 A-B 3 1 Generation of Diagnostic Tree Backtracing of test step 1 Time frame 3 Time frame 2 Time frame 1

Research in ATI © Raimund Ubar 47 OPOP LDA0AC=M AND1 AC=AC  M ADD2 AC=AC  M SUB3 AC=AC  M JMP4PC=A STA5M=AC JSR6 PC=A Jump to subroutine Parwan: Instruction Set OPIP CLA701AC=0 CMA702 AC=  AC CMC704 C=  C ASL708AC=2AC ASR709AC=AC/2 BRA_N710If negative BRA_Z712If zero BRA_C714If carry BRA_V718If overflow

Research in ATI © Raimund Ubar PC_A P1P1 OP 1 A1A1 PC_A + 2 P2P2 N A2A2 I ,6 0-3, OP PC_A + 1 OP 2 7 PC_A 6 Z C V PC_A Next PC offset calculation Instruction addressing OP. I. P LOC(PC_A ) PC_P PC_A A LOC(PC_A+1 ) PC_P PC_A PC_P OP 1 P1P1 4 PC_P Next memory page calculation ALU Flags OP N I N F N (AC,M’) P 2,8,9 F c2 (AC) C V OP C I 2,3 0 7 F c1 (AC,M’) P 4,8 F c2 (AC) OP V I 2,3 0 7 F v1 (AC,M’) P 8 F v2 (AC) OP Z I Z F z (AC,M’) P 2,8,9 F c2 (AC) Output behaviour M’ (A) OP 5 AC M’ P A LOC(A ) Direct addressing LOC(M’) P M’’ M’ 0-15 Indirect addressing ALU Data Path AC P1P1 OP 1 M’ AC & M’ AC + M’ AC - M’ AC P3P3 00 I OP M’’ OP 2 1 AC AC/  AC 2AC 4  AC Parwan: HLDD Model

Research in ATI © Raimund Ubar 49 OP N I N F N (AC,M’) P 2,8,9 F c2 (AC) Formal Test Generation for Parwan Test program template LDA AND <Cycle over data instr> BRA_N <Cycle over br. instr> ADD STA <Test response propag> AC P1P1 OP 1 M’ AC & M’ AC + M’ AC - M’ AC I PC_A P N A I 1 7 OP 1 0 Z C V PC_A OP = 5 I = 0 P = 0 AC STA AC 2 M = const OP = 2 I = 0 P = 0 ADD OP = 7 I = 1 P = 0 BRA_N N AC 1 PC_A Next instr Jump OP = 1 I = 0 P = 0 AND AC OP = 0 I = 0 P = 0 LDA M2 AC 1 M1 M3 From data array Cycle over branch instr P = 0,2,4,6 Cycle over data instr. OP = 0,1,2,3 Data initialization Response propagation

Research in ATI © Raimund Ubar 50 Test Program for Parwan Microrocessor FOR VAR1 = 0, 1, 2, 4, 8, 9(For all single byte ALU instructions) FOR VAR2 = 0, 2, 4,… N(For all data operands) FOR VAR3 = 0, 2, 4, 8(For all branch operations) k) LDA, VAR2 (Data initialization) k+2) I=0, P=0, OP = VAR1(ALU Test, Flag initialization) k+3) I=1, P=VAR3, OP=7(Branch Test) k+4) m(Jump address for fixing AC1 = AC) k+5) ADD, CONST(Fixing AC2  AC1) k+7) ADD, LOC (REF)(Signature calculated: REF = REF + AC1) k+9) STA, LOC (REF)(Finish: Signature updated) END VAR3 END VAR2 END VAR1 m)ADD, LOC (REF)(Signature calculated: REF = REF + AC2) m+2)JMP, k+9