Overview of Chapter 4 °Design digital circuit from specification °Digital inputs and outputs known Need to determine logic that can transform data °Start in truth table form °Create K-map for each output based on function of inputs °Determine minimized sum-of-product representation °Draw circuit diagram

Design Procedure (Mano) Design a circuit from a specification. 1.Determine number of required inputs and outputs. 2.Derive truth table 3.Obtain simplified Boolean functions 4.Draw logic diagram and verify correctness A A B B C C R R S S S = A + B + C R = ABC

Previously, we have learned… °Boolean algebra can be used to simplify expressions, but not obvious: how to proceed at each step, or if solution reached is minimal. °Have seen five ways to represent a function: Boolean expression truth table logic circuit minterms/maxterms Karnaugh map

Combinational logic design °Use multiple representations of logic functions °Use graphical representation to assist in simplification of function. °Use concept of “don’t care” conditions. °Example - encoding BCD to seven segment display. °Similar to approach used by designers in the field.

BCD to Seven Segment Display °Used to display binary coded decimal (BCD) numbers using seven illuminated segments. °BCD uses 0’s and 1’s to represent decimal digits Need four bits to represent required 10 digits. °Binary coded decimal (BCD) represents each decimal digit with four bits a b c g e d f

BCD to seven segment display 0a,b,c,d,e,f 1b,c 2a,b,d,e,g 3a,b,c,d,g 4b,c,f,g 5a,c,d,f,g 6a,c,d,e,f,g 7a,b,c 8a,b,c,d,e,f,g 9a,b,c,d,f,g a b c g e d f °List the segments that should be illuminated for each digit.

BCD to seven segment display edcbazyxwDec  °Derive the truth table for the circuit. °Each output column in one circuit. InputsOutputs

BCD to seven segment display yz wx For segment “a” : Note: Have only filled in ten squares, corresponding to the ten numerical digits we wish to represent. °Find minimal sum-of-products representation for each output

Don’t care conditions (BCD display) XX XXXX yz wx For segment “a” : Put in “X” (don’t care), and interpret as either 1 or 0 as desired …. °Fill in don’t cares for undefined outputs. Note that these combinations of inputs should never happen. °Leads to a reduced implementation

Don’t care conditions (BCD display)... For segment “a” : XX XXXX yz wx °Circle biggest group of 1’s and Don’t Cares. °Leads to a reduced implementation

Don’t care conditions (BCD display) For segment “a” : XX XXXX yz wx °Circle biggest group of 1’s and Don’t Cares. °Leads to a reduced implementation

Don’t care conditions (BCD display)... For segment “a” : XX XXXX yz wx XX XXXX yz wx °Circle biggest group of 1’s and Don’t Cares. °All 1’s should be covered by at least one implicant

Don’t care conditions (BCD display)... For segment “a” : XX XXXX yz wx ° Put all the terms together °Generate the circuit

BCD to seven segment display edcbazyxwDec  °Derive the truth table for the circuit. °Each output column in one circuit. InputsOutputs

BCD to seven segment display yz wx For segment “b” : See if you complete this example. °Find minimal sum-of-products representation for each output

Half Adder CABS 0001 A 0 B 0 S 0 C Dec Binary °Add two binary numbers A 0, B 0 -> single bit inputs S 0 -> single bit sum C 1 -> carry out

Multiple-bit Addition A 3 A 2 A 1 A A B 3 B 2 B 1 B 0 B A B A i +B i C i SiSi C i+1 °Consider single-bit adder for each bit position. Each bit position creates a sum and carry

Full Adder C i A i B i S i C i CiCi AiBiAiBi SiSi °Full adder includes carry in C i °Notice interesting pattern in Karnaugh map.

Full Adder C i A i B i S i C i+1 S i = !C i & !A i & B i # !C i & A i & !B i # C i & !A i & !B i # C i & A i & B i °Full adder includes carry in C i °Alternative to XOR implementation

Full Adder &:and, #:or, $: xor S i = !C i & !A i & B i # !C i & A i & !B i # C i & !A i & !B i # C i & A i & B i S i = !C i & (!A i & B i # A i & !B i ) # C i & (!A i & !B i # A i & B i ) S i = !C i & (A i $ B i ) # C i & !(A i $ B i ) S i = C i $ (A i $ B i ) °Reduce and/or representations into XORs

Full Adder C i A i B i S i C i CiCi AiBiAiBi C i+1 °Now consider implementation of carry out °Two outputs per full adder bit (C i+1, S i ) Note: 3 inputs

Full Adder C i A i B i S i C i+1 CiCi AiBiAiBi C i+1 C i+1 = A i & B i # C i & B i # C i & A i °Now consider implementation of carry out °Minimize circuit for carry out - C i+1

Full Adder C i+1 = A i & B i # C i !A i & B i # C i & A i & !B i C i+1 = A i & B i # C i & (!A i & B i # A i & !B i ) C i+1 = A i & B i # C i & (A i $ B i ) Recall: S i = C i $ (A i $ B i ) C i+1 = A i & B i # C i & (A i $ B i )

Full Adder S i = C i $ (A i $ B i ) Half-adder C i+1 = A i & B i # C i & (A i $ B i ) °Full adder made of several half adders

Full Adder A full adder can be made from two half adders (plus an OR gate). °Hardware repetition simplifies hardware design

Full Adder Block Diagram °Putting it all together Single-bit full adder Common piece of computer hardware

4-Bit Adder C A B S °Chain single-bit adders together. °What does this do to delay?

Negative Numbers – 2’s Complement = = = FF 16 = = = = = °Subtracting a number is the same as: 1.Perform 2’s complement 2.Perform addition °If we can augment adder with 2’s complement hardware?

4-bit Subtractor: E = 1 +1 Add A to B’ (one’s complement) plus 1 That is, add A to two’s complement of B D = A - B

Adder- Subtractor Circuit

Overflow in two’s complement addition °Definition: When two values of the same signs are added: Result won’t fit in the number of bits provided Result has the opposite sign. Overflow? C N-1 CNCN Assumes an N-bit adder, with bit N-1 the MSB

Addition cases and overflow OFL

Magnitude Comparator °The comparison of two numbers outputs: A>B, A=B, A<B °Design Approaches the truth table -2 2n entries - too cumbersome for large n use inherent regularity of the problem -reduce design efforts -reduce human errors Magnitude Compare A[3..0] B[3..0] A = B A < B A > B

Magnitude Comparator How can we find A > B? How many rows would a truth table have? 2 8 = 256

Magnitude Comparator If A = 1001 and B = 0111 is A > B? Why? Because A3 > B3 i.e. A3. B3’ = 1 Therefore, one term in the logic equation for A > B is A3. B3’ Find A > B

Magnitude Comparator If A = 1010 and B = 1001 is A > B? Why? Because A3 = B3 and A2 = B2 and A1 > B1 i.e. C3 = 1 and C2 = 1 and A1. B1’ = 1 Therefore, the next term in the logic equation for A > B is C3. C2. A1. B1’ A > B = A3. B3’ + C3. A2. B2’ + …..

Magnitude Comparison °Algorithm -> logic A = A 3 A 2 A 1 A 0 ; B = B 3 B 2 B 1 B 0 A=B if A 3 =B 3, A 2 =B 2, A 1 =B 1 and A 0 =B 0 °Test each bit: -equality: x i = A i B i +A i 'B i ' -(A=B) = x 3 x 2 x 1 x 0 °More difficult to test less than/greater than (A>B) = A 3 B 3 '+x 3 A 2 B 2 '+x 3 x 2 A 1 B 1 '+x 3 x 2 x 1 A 0 B 0 ' (A<B) = A 3 'B 3 +x 3 A 2 'B 2 +x 3 x 2 A 1 'B 1 +x 3 x 2 x 1 A 0 'B 0 Start comparisons from high-order bits °Implementation x i = (A i B i '+A i 'B i )’

Magnitude Comparison °Hardware chips

Magnitude Comparator °Real-world application Thermostat controller

Multiplexers °Select an input value with one or more select bits °Use for transmitting data °Allows for conditional transfer of data °Sometimes called a mux

4– to– 1- Line Multiplexer

Quadruple 2–to–1-Line Multiplexer °Notice enable bit °Notice select bit °4 bit inputs

Multiplexer as combinational modules °Connect input variables to select inputs of multiplexer (n-1 for n variables) °Set data inputs to multiplexer equal to values of function for corresponding assignment of select variables °Using a variable at data inputs reduces size of the multiplexer

Implementing a Four- Input Function with a Multiplexer

Typical multiplexer uses

Three-state gates A multiplexer can be constructed with three-state gates Output state: 0, 1, and high-impedance (open ckts) If the select input (E) is 0, the three-state gate has no output Opposite true here, No output if E is 1

Three-state gates A multiplexer can be constructed with three-state gates Output state: 0, 1, and high-impedance (open ckts) If the select input is low, the three-state gate has no output

Decoders and Encoders °Binary decoders Converts an n-bit code to a single active output Can be developed using AND/OR gates Can be used to implement logic circuits. °Binary encoders Converts one of 2 n inputs to an n-bit output Useful for compressing data Can be developed using AND/OR gates °Both encoders and decoders are extensively used in digital systems

Binary Decoder °Black box with n input lines and 2 n output lines °Only one output is a 1 for any given input Binary Decoder n inputs 2 n outputs

2-to-4 Binary Decoder °From truth table, circuit for 2x4 decoder is: °Note: Each output is a 2- variable minterm (X'Y', X'Y, XY' or XY) F 0 = X'Y' F 1 = X'Y F 2 = XY' F 3 = XY XY Truth Table: 2-to-4 Decoder X Y F0 F1 F2 F3

3-to-8 Binary Decoder F 1 = x'y'z xzy F 0 = x'y'z' F 2 = x'yz' F 3 = x'yz F 5 = xy'z F 4 = xy'z' F 6 = xyz' F 7 = xyz Truth Table: 3-to-8 Decoder X Y F0 F1 F2 F3 F4 F5 F6 F7 Z

Implementing Functions Using Decoders °Any n-variable logic function can be implemented using a single n-to-2 n decoder to generate the minterms OR gate forms the sum. The output lines of the decoder corresponding to the minterms of the function are used as inputs to the or gate. °Any combinational circuit with n inputs and m outputs can be implemented with an n-to-2 n decoder with m OR gates. °Suitable when a circuit has many outputs, and each output function is expressed with few minterms.

Implementing Functions Using Decoders °Example: Full adder S(x, y, z) =  (1,2,4,7) C(x, y, z) =  (3,5,6,7) 3-to-8 Decoder S2S1S0S2S1S0 x y z S C

Standard MSI Binary Decoders Example (3-to-8 decoder) (a) Logic circuit. (b) Package pin configuration. (c) Function table.

Building a Binary Decoder with NAND Gates °Start with a 2-bit decoder Add an enable signal (E) Note: use of NANDs only one 0 active! if E = 0

Use two 3 to 8 decoders to make 4 to 16 decoder °Enable can also be active high °In this example, only one decoder can be active at a time. °x, y, z effectively select output line for w

Encoders °If the a decoder's output code has fewer bits than the input code, the device is usually called an encoder. e.g. 2 n -to-n °The simplest encoder is a 2 n -to-n binary encoder O ne of 2 n inputs = 1 Output is an n-bit binary number n inputs n outputs Binary encoder

8-to-3 Binary Encoder At any one time, only one input line has a value of I0I1I2I3I4I5I6I7I0I1I2I3I4I5I6I7 y 0 = I 1 + I 3 + I 5 + I 7 y 1 = I 2 + I 3 + I 6 + I 7 y 2 = I 4 + I 5 + I 6 + I 7

8-to-3 Priority Encoder What if more than one input line has a value of 1? Ignore “lower priority” inputs. Idle indicates that no input is a 1. Note that polarity of Idle is opposite from Table 4-8 in Mano

Priority Encoder (8 to 3 encoder) °Assign priorities to the inputs °When more than one input are asserted, the output generates the code of the input with the highest priority °Priority Encoder : H7=I7 (Highest Priority) H6=I6.I7’ H5=I5.I6’.I7’ H4=I4.I5’.I6’.I7’ H3=I3.I4’.I5’.I6’.I7’ H2=I2.I3’.I4’.I5’.I6’.I7’ H1=I1. I2’.I3’.I4’.I5’.I6’.I7’ H0=I0.I1’. I2’.I3’.I4’.I5’.I6’.I7’ IDLE= I0’.I1’. I2’.I3’.I4’.I5’.I6’.I7’ °Encoder Y0 = I1 + I3 + I5 + I7 Y1 = I2 + I3 + I6 + I7 Y2 = I4 + I5 + I6 + I7 Y1 Y2 Y0 IDLE I1 I2 I3Y1 Y2I4 I5 I6 I0 Y0 I7 Binary encoder I1 I2 I3 I4 I5 I6 I0 I7 Priority Circuit H1 H2 H3 H4 H5 H6 H0 H7 IDLE I1 I2 I3 I4 I5 I6 I0 I7 Priority encoder

Encoder Application (Monitoring Unit) Action EncoderController Machine Code Machine 1 Machine 2 Machine n Alarm Signal Contoller Response °Encoder identifies the requester and encodes the value °Controller accepts digital inputs.