Combinational Logic Chapter 4

Digital Circuits Combinational Circuits Logic circuits for digital system Combinational circuits the outputs are a function of the current inputs Sequential circuits contain memory elements the outputs are a function of the current inputs and the state of the memory elements the outputs also depend on past inputs

Digital Circuits 3 A combinational circuits 2 n possible combinations of input values Specific functions Adders, subtractors, comparators, decoders, encoders, and multiplexers MSI circuits or standard cells Combinational Logic Circuit n input variables m output variables

Digital Circuits Analysis Procedure A combinational circuit make sure that it is combinational not sequential No feedback path derive its Boolean functions (truth table) design verification a verbal explanation of its function

Digital Circuits 5 A straight-forward procedure F 2 = AB+AC+BC T 1 = A+B+C T 2 = ABC T 3 = F 2 'T 1 F 1 = T 3 +T 2

Digital Circuits 6 F 1 = T 3 +T 2 = F 2 'T 1 +ABC = (AB+AC+BC)'(A+B+C)+ABC = (A'+B')(A'+C')(B'+C')(A+B+C)+ABC = (A'+B'C')(AB'+AC'+BC'+B'C)+ABC = A'BC'+A'B'C+AB'C'+ABC A full-adder F 1 : the sum F 2 : the carry

Digital Circuits 7 The truth table

Digital Circuits Design Procedure The design procedure of combinational circuits State the problem (system spec.) determine the inputs and outputs the input and output variables are assigned symbols derive the truth table derive the simplified Boolean functions draw the logic diagram and verify the correctness

Digital Circuits 9 Functional description Boolean function HDL (Hardware description language) Verilog HDL VHDL Schematic entry Logic minimization number of gates number of inputs to a gate propagation delay number of interconnection limitations of the driving capabilities

Digital Circuits 10 Code conversion example BCD to excess-3 code The truth table

Digital Circuits 11 The maps

Digital Circuits 12 The simplified functions z = D' y = CD +C'D' x = B'C + B'D+BC'D' w = A+BC+BD Another implementation z = D' y = CD +C'D'= CD + (C+D)' x = B'C + B'D+BC'D‘ = B'(C+D) +B(C+D)' w = A+BC+BD

Digital Circuits 13 The logic diagram

Digital Circuits Binary Adder-Subtractor Half adder 0+0=0 ; 0+1=1 ; 1+0=1 ; 1+1=10 two input variables: x, y two output variables: C (carry), S (sum) truth table

Digital Circuits 15 S = x'y+xy' C = xy the flexibility for implementation S=x  y S = (x+y)(x'+y') S' = xy+x'y' S = (C+x'y')' C = xy = (x'+y')'

Digital Circuits 16

Digital Circuits 17 Full-Adder The arithmetic sum of three input bits three input bits x, y: two significant bits z: the carry bit from the previous lower significant bit Two output bits: C, S

Digital Circuits 18

Digital Circuits 19 S = x'y'z+x'yz'+ xy'z'+xyz C = xy + xz + yz S = z  (x  y) = z'(xy'+x'y)+z(xy'+x'y)' = z'xy'+z'x'y+z((x'+y)(x+y')) = xy'z'+x'yz'+xyz+x'y'z C = z(xy'+x'y)+xy = xy'z+x'yz+ xy

Digital Circuits 20 Binary adder

Digital Circuits 21 Carry propagation when the correct outputs are available the critical path counts (the worst case) (A 1,B 1,C 1 ) > C 2 > C 3 > C 4 > (C 5,S 4 ) > 8 gate levels

Digital Circuits 22 Reduce the carry propagation delay employ faster gates look-ahead carry (more complex mechanism, yet faster) carry propagate: P i = A i  B i carry generate: G i = A i B i sum: S i = P i  C i carry: C i+1 = G i +P i C i C 1 = G 0 +P 0 C 0 C 2 = G 1 +P 1 C 1 = G 1 +P 1 (G 0 +P 0 C 0 ) = G 1 +P 1 G 0 +P 1 P 0 C 0 C 3 = G 2 +P 2 C 2 = G 2 +P 2 G 1 +P 2 P 1 G 0 + P 2 P 1 P 0 C 0

Digital Circuits 23 Logic diagram

Digital Circuits 24 4-bit carry-look ahead adder propagation delay

Digital Circuits 25 Binary subtractor A-B = A+(2’s complement of B) 4-bit Adder-subtractor M=0, A+B; M=1, A+B’+1

Digital Circuits 26 Overflow The storage is limited Add two positive numbers and obtain a negative number Add two negative numbers and obtain a positive number V=0, no overflow; V=1, overflow

Digital Circuits Decimal Adder Add two BCD's 9 inputs: two BCD's and one carry-in 5 outputs: one BCD and one carry-out Design approaches A truth table with 2^9 entries use binary full Adders the sum <= = 19 binary to BCD

Digital Circuits 28 The truth table

Digital Circuits 29 Modifications are needed if the sum > 9 C = 1 K = 1 Z 8 Z 4 = 1 Z 8 Z 2 = 1 modification: -(10) d or +6

Digital Circuits 30 Block diagram

Digital Circuits 31 Binary Multiplier Partial products – AND operations

Digital Circuits 32 4-bit by 3-bit binary multiplier

Digital Circuits Magnitude Comparator The comparison of two numbers outputs: A>B, A=B, A<B Design Approaches the truth table 2 2n entries - too cumbersome for large n use inherent regularity of the problem reduce design efforts reduce human errors

Digital Circuits 34 Algorithm -> logic A = A 3 A 2 A 1 A 0 ; B = B 3 B 2 B 1 B 0 A=B if A 3 =B 3, A 2 =B 2, A 1 =B 1 and A 1 =B 1 equality: x i = A i B i +A i 'B i ' (A=B) = x 3 x 2 x 1 x 0 (A>B) = A 3 B 3 '+x 3 A 2 B 2 '+x 3 x 2 A 1 B 1 '+x 3 x 2 x 1 A 0 B 0 ' (A>B) = A 3 'B 3 +x 3 A 2 'B 2 +x 3 x 2 A 1 'B 1 +x 3 x 2 x 1 A 0 'B 0 Implementation x i = (A i B i '+A i 'B i )'

Digital Circuits 35

Digital Circuits Decoder A n-to-m decoder a binary code of n bits = 2 n distinct information n input variables; up to 2 n output lines only one output can be active (high) at any time

Digital Circuits 37 An implementation

Digital Circuits 38 Combinational logic implementation each output = a minterm use a decoder and an external OR gate to implement any Boolean function of n input variables

Digital Circuits 39 Demultiplexers a decoder with an enable input receive information on a single line and transmits it on one of 2 n possible output lines

Digital Circuits 40 Decoder/demultiplexers

Digital Circuits 41 Expansion two 3-to-8 decoder: a 4-to-16 deocder a 5-to-32 decoder?

Digital Circuits 42 Combination Logic Implementation each output = a minterm use a decoder and an external OR gate to implement any Boolean function of n input variables A full-adder S(x,y,x)=  (1,2,4,7) C(x,y,z)=  (3,5,6,7)

Digital Circuits 43 two possible approaches using decoder OR(minterms of F): k inputs NOR(minterms of F'): 2 n - k inputs In general, it is not a practical implementation

Digital Circuits Encoders The inverse function of a decoder

Digital Circuits 45 An implementation limitations illegal input: e.g. D 3 =D 6 =1 the output = 111 (¹3 and ¹6)

Digital Circuits 46 Priority Encoder resolve the ambiguity of illegal inputs only one of the input is encoded D 3 has the highest priority D 0 has the lowest priority X: don't-care conditions V: valid output indicator

Digital Circuits 47

Digital Circuits Multiplexers select binary information from one of many input lines and direct it to a single output line 2 n input lines, n selection lines and one output line e.g.: 2-to-1-line multiplexer

Digital Circuits 49 4-to-1-line multiplexer

Digital Circuits 50 Note n-to- 2 n decoder add the 2 n input lines to each AND gate OR(all AND gates) an enable input (an option)

Digital Circuits 51

Digital Circuits 52 Boolean function implementation MUX: a decoder + an OR gate 2 n -to-1 MUX can implement any Boolean function of n input variable a better solution: implement any Boolean function of n+1 input variable n of these variables: the selection lines the remaining variable: the inputs

Digital Circuits 53 an example: F(A,B,C)=  (1,3,5,6)

Digital Circuits 54 Procedure: assign an ordering sequence of the input variable the leftmost variable (A) will be used for the input lines assign the remaining n-1 variables to the selection lines w.r.t. their corresponding sequence list all the minterms in two rows (A' and A) circle all the minterms of the function determine the input lines

Digital Circuits 55 An example: F(A,B,C,D)=  (0,1,3,4,8,9,15)

Digital Circuits 56 It is possible to use any other variable of the function for the MUX data inputs

Digital Circuits 57 Three-state gates A multiplexer can be constructed with three-state gates Output state: 0, 1, and high-impedance (open ckts)