Programmable Logic Circuits: Computer Arithmetic: Introduction Dr. Eng. Amr T. Abdel-Hamid ELECT 90X Fall 2009 Slides based on slides prepared by: B. Parhami, Computer Arithmetic: Algorithms and Hardware Design, Oxford University Press, I. Koren, Computer Arithmetic Algorithms, 2nd Edition, A.K. P eters, Natick, MA, 2002.

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits What is Computer Arithmetic? Pentium Division Bug ( ): Pentium’s radix-4 SRT algorithm occasionally gave incorrect quotient First noted in 1994 by T. Nicely who computed sums of re ciprocals of twin primes: 1/5 + 1/7 + 1/11 + 1/ /p + 1/(p + 2) +... Worst-case example of division error in Pentium:

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Using a calculator with √, x 2, and x y functions, compute: u = √√ … √ 2 = “1024th root of 2” v = 2 1/1024 = Save u and v; If you ca n’t save, recompute values when needed x = (((u 2 ) 2 )...) 2 = x' = u 1024 = y = (((v 2 ) 2 )...) 2 = y' = v 1024 = Perhaps v and u are not really the same value w = v – u = 1  10 –11 Nonzero due to hidden digits (u – 1)  1000 = [Hidden... (0) 68] (v – 1)  1000 = [Hidden... (0) 69] A Motivating Example

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Finite Range Can Lead to Disaster Example: Explosion of Ariane Rocket (1996 J une 4) Unmanned Ariane 5 rocket of the European Space Agency v eered off its flight path, broke up, and exploded only 30 s after lift-off (altitude of 3700 m) The $500 million rocket (with cargo) was on its first voyage after a decade of development costing $7 billion Cause: “software error in the inertial reference system” Problem specifics: A 64 bit floating point number relating to the horizontal velocity of the rocket was being convert ed to a 16 bit signed integer An SRI* software exception arose during conversion becaus e the 64-bit floating point number had a value greater th an what could be represented by a 16-bit signed integer (max ) *SRI = Inertial Reference System

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Encoding Numbers in 4 Bits Some of the possible ways of assigning 16 distinct codes to represent n umbers.

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits The Binary Number System  In conventional digital computers - integers repr esented as binary numbers of fixed length n  An ordered sequence of bi nary digits  Each digit x (bit) is 0 or 1  The above sequence represents the integer value X  Upper case letters represent numerical values or s equences of digits  Lower case letters, usually indexed, represent indi vidual digits i

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Radix of a Number System  The weight of the digit x is the i th power of 2  2 is the radix of the binary number system  Binary numbers are radix-2 numbers - allowed digits are 0,1  Decimal numbers are radix-10 numbers - allo wed digits are 0,1,2,…,9  Radix indicated in subscript as a decimal numb er  Example:  (101) - decimal value 101  (101) - decimal value 5 i 10 2

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Range of Representations  Operands and results are stored in registers of fixed length n - finite number of distinct value s that can be represented within an arithmetic unit  X min ; X max - smallest and largest representab le values  [X min,X max] - range of the representable num bers  A result larger then X max or smaller than X min - incorrectly represented  The arithmetic unit should indicate that the ge nerated result is in error - an overflow indica tion

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Example - Overflow in Binary System  Unsigned integers with 5 binary digits (bits)  X max = (31) 10 - represented by (11111) 2  X min = (0) 10 - represented by (00000) 2  Increasing X max by 1 = (32) 10 =(100000) 2  5-bit representation - only the last five digits retained - yielding (00000) 2 =(0) 10  In general -  A number X not in the range [Xmin,Xmax]=[0,31] is represented by X mod 32  If X+Y exceeds X max - the result is S = (X+Y) mod 32  Example: X Y = 35 mod 32  Result has to be stored in a 5-bit register - the most signif icant bit (with weight 2 =32) is discarded 5

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Fixed Radix Systems  r - the radix of the number system  Conventional number systems are also called fix ed-radix systems  With no redundancy - 0  x i  r-1  x i  r introduces redundancy into the fixed-radix number system ?? HOW?  If x i  r is allowed -  two machine representations for the same value -(..., x i+ 1, x i,... ) and (..., x i+ 1 +1, x i -r,... )

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Representation of Mixed Numbers  A sequence of n digits in a register - not necessa rily representing an integer  Can represent a mixed number with a fractional part and an integral part  The n digits are partitioned into two - k in the in tegral part and m in the fractional part (k+m=n)  The value of an n-tuple with a radix point betwee n the k most significant digits and the m least sig nificant digits  is

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Fixed Point Representations  Radix point not stored in register - understood to be in a fix ed position between the k most significant digits and the m least significant digits  These are called fixed-point representations  Programmer not restricted to the predetermined position of the radix point  Operands can be scaled - same scaling for all operands  Add and subtract operations are correct -  aX  aY=a(X  Y) (a - scaling factor)  Corrections required for multiplication and division  aX  aY=a X  Y ; aX/aY=X/Y  Commonly used positions for the radix point -  rightmost side of the number (pure integers - m=0)  leftmost side of the number (pure fractions - k=0) 2

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits ULP - Unit in Last Position  Given the length n of the operands, the weigh t r of the least significant digit indicates the position of the radix point  Unit in the last position (ulp) - the weight of t he least significant digit  ulp = r  This notation simplifies the discussion  No need to distinguish between the different p artitions of numbers into fractional and integr al parts -m

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Representation of Negative Numbers  Fixed-point numbers in a radix r system  Two ways of representing negative numbers:  Sign and magnitude representation (or signed- magnitude representation)  Complement representation with two alternative s  Radix complement (two's complement in the binary system)  Diminished-radix complement (one's comple ment in the binary system)

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Signed-Magnitude Representation  Sign and magnitude are represented separately  First digit is the sign digit, remaining n-1 digits repre sent the magnitude  Binary case - sign bit is 0 for positive, 1 for negative numbers  Non-binary case - 0 and r-1 indicate positive and ne gative numbers  Only 2r out of the r possible sequences are utili zed  Two representations for zero - positive and negative  Inconvenient when implementing an arithmetic un it - when testing for zero, the two different repre sentations must be checked n -1 n

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Disadvantage of the Signed-Magnitude Representation  Operation may depend on the signs of the operands  Example - adding a positive number X and a negative num ber -Y : X+(-Y)  If Y>X, final result is -(Y-X)  Calculation -  switch order of operands  perform subtraction rather than addition  attach the minus sign  A sequence of decisions must be made, costing excess con trol logic and execution time  This is avoided in the complement representation methods

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Complement Representations of Negative Numbers  Two alternatives -  Radix complement (called two's complemen t in the binary system)  Diminished-radix complement (called one's c omplement in the binary system)  In both complement methods - positive numbe rs represented as in the signed-magnitude met hod  A negative number -Y is represented by R-Y w here R is a constant  This representation satisfies -(-Y )=Y since R -(R-Y)=Y

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Advantage of Complement Representation  No decisions made before executing addition o r subtraction  Example: X-Y=X+(-Y)  -Y is represented by R-Y  Addition is performed by X+(R-Y) = R-(Y-X)  If Y>X, -(Y-X) is already represented as R-(Y- X)  No need to interchange the order of the two o perands

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Two’s Complement  r=2, k=n=4, m=0, ulp=2 =1  Radix complement (called two's complement in the binary c ase) of a number X = 2 - X  It can instead be calculated by X+1  0000 to 0111 represent positive numbers 0 10 to 7 10  The two's complement of 0111 is =1001  it represents the value (-7) 10  The two's complement of 0000 is =10000=0 mod 2 - single representation of zero  Each positive number has a corresponding negative number that starts with a 1  1000 representing (-8) 10 has no corresponding positive num ber  Range of representable numbers is -8  X 

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits The Two’s Complement Representation

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Example - Addition in Two’s complement  Calculating X+(-Y) with Y>X - 3+(-5)  Correct result represented in the two's comple ment method - no need for preliminary decision s or post corrections  Calculating X+(-Y) with X>Y - 5+(-3)   Only the last four least significant digits are ret ained, yielding 0010

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits One’s Complement in Binary System  r=2, k=n=4, m=0, ulp=2 =1  Diminished-radix complement (called one's com plement in the binary case) of a number X = (2 - 1) - X = X  As before, the sequences 0000 to 0111 represen t the positive numbers 0 10 to 7 10  The one's complement of 0111 is 1000, represe nting (-7) 10  The one's complement of zero is two rep resentations of zero  Range of representable numbers is -7  X 

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Comparing the Three Representations in a Binary System

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits 5.1 Bit-Serial and Ripple-Carry Adders Half-adder (HA): Truth table and block diagram Full-adder (FA): Truth table and block diagram

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Half-Adder Implementations Three implementations of a half-adder. c

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Full-Adder Implementations Possible designs for a full-adder in terms of half-adders, logic gates, and CMOS transmission gates.

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Full-Adder Details CMOS transmission gate and its use in a 2-to-1 mux. Logic equations for a full-adder: s= x  y  c in (odd parity function) = x y c in  x y  c in  x  y c in  x y  c in c out = x y  x c in  y c in (majority function)

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Simple Adders Built of Full-Adders Using full-adders in building bit-serial and ripple-carry adders.

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Critical Path Through a Ripple-Carry Adder Critical path in a k-bit ripple-carry adder. T ripple-add = T FA (x,y  c out ) + (k – 2)  T FA (c in  c out ) + T FA (c in  s)

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Binary Adders as Versatile Building Blocks Four-bit binary adder used to realize the logic function f = w + xyz and its complement. Set one input to 0:c out = AND of other inputs Set one input to 1:c out = OR of other inputs Set one input to 0 and another to 1: s = NOT of third input

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Conditions and Exceptions Two’s-complement adder with provisions for detecting conditions and exceptions. overflow 2’s-compl = c k  c k–1 = c k  c k–1  c k c k–1

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Manchester Carry Chains and Adders Sum digit in radix rs i =(x i + y i + c i ) mod r Special case of radix 2s i =x i  y i  c i Computing the carries c i is thus our central problem For this, the actual operand digits are not important What matters is whether in a given position a carry is generated, propagated, or annihilated (absorbed) For binary addition: g i = x i y i p i = x i  y i a i =  x i y i = (x i  y i ) It is also helpful to define a transfer signal: t i = g i  p i = a i = x i  y i Using these signals, the carry recurrence is written as c i+1 = g i  c i p i = g i  c i g i  c i p i = g i  c i t i

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Carry Network is the Essence of a Fast Adder The main part of an adder is the carry network. The rest is just a set of gates to produce the g and p signals and the sum bits. g i = x i y i p i = x i  y i Ripple; Skip; Lookahead; Parallel-prefix

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Ripple-Carry Adder Revisited The carry propagation network of a ripple-carry adder. The carry recurrence: c i+1 = g i  p i c i Latency of k-bit adder is roughly 2k gate delays: 1 gate delay for production of p and g signals, plus 2(k – 1) gate delays for carry propagation, plus 1 XOR gate delay for generation of the sum bits

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits The Complete Design of a Ripple-Carry Adder g i = x i y i p i = x i  y i

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Unrolling the Carry Recurrence Recall the generate, propagate, annihilate (absorb), and transfer signals: SignalRadix rBinary g i is 1 iff x i + y i  r x i y i p i is 1 iff x i + y i = r – 1 x i  y i a i is 1 iff x i + y i < r – 1 x i y i = (x i  y i ) t i is 1 iff x i + y i  r – 1x i  y i s i (x i + y i + c i ) mod rx i  y i  c i The carry recurrence can be unrolled to obtain each carry signal directly from inputs, rather than through propagation c i = g i–1  c i–1 p i–1 = g i–1  (g i–2  c i–2 p i–2 ) p i–1 = g i–1  g i–2 p i–1  c i–2 p i–2 p i–1 = g i–1  g i–2 p i–1  g i–3 p i–2 p i–1  c i–3 p i–3 p i–2 p i–1 = g i–1  g i–2 p i–1  g i–3 p i–2 p i–1  g i–4 p i–3 p i–2 p i–1  c i–4 p i–4 p i–3 p i–2 p i–1 =...

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Full Carry Lookahead Theoretically, it is possible to derive each sum digit directly from the inputs that affect it Carry-lookahead adder design is simply a way of reducing the complexity of this ideal, but impractical, arrangement by hardware sharing among the various lookahead circuits s0s0 s1s1 s2s2 s3s3 y0y0 y1y1 y2y2 y3y3 x0x0 x1x1 x2x2 x3x3 c in...

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Four-Bit Carry-Lookahead Adder Complexity reduced by deriving the carry-out indirectly Four-bit carry network with full lookahead. Full carry lookahead is quite practical for a 4-bit adder c 1 = g 0  c 0 p 0 c 2 = g 1  g 0 p 1  c 0 p 0 p 1 c 3 = g 2  g 1 p 2  g 0 p 1 p 2  c 0 p 0 p 1 p 2 c 4 = g 3  g 2 p 3  g 1 p 2 p 3  g 0 p 1 p 2 p 3  c 0 p 0 p 1 p 2 p 3

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Carry Lookahead Beyond 4 Bits 32-input AND Consider a 32-bit adder c 1 = g 0  c 0 p 0 c 2 = g 1  g 0 p 1  c 0 p 0 p 1 c 3 = g 2  g 1 p 2  g 0 p 1 p 2  c 0 p 0 p 1 p 2. c 31 = g 30  g 29 p 30  g 28 p 29 p 30  g 27 p 28 p 29 p 30 ...  c 0 p 0 p 1 p 2 p 3... p 29 p input OR... High fan-ins necessitate tree-structured circuits

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Solutions to the Fan-in Problem Multilevel lookahead Block Adders High-radix addition (i.e., radix 2 h ) : Increases the latency for generating g and p signals and sum digits, but simplifies the carry network (optimal radix?) Example: 16-bit addition Radix-16 (four digits) Two-level carry lookahead (four 4-bit blocks) Either way, the carries c 4, c 8, and c 12 are determined first c 16 c 15 c 14 c 13 c 12 c 11 c 10 c 9 c 8 c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 C out ? ? ? c in

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Block Ripple Adder

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Larger Carry-Lookahead Adder Design Block generate and propagate signals g [i,i+3] = g i+3  g i+2 p i+3  g i+1 p i+2 p i+3  g i p i+1 p i+2 p i+3 p [i,i+3] = p i p i+1 p i+2 p i+3 If all 4 bits in a block propagate, the block propagates a carry. If at least one of the 4 bits generates carry and it can be propagated to the MSB, the block generates a carry.

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits A Building Block for Carry-Lookahead Addition Four-bit lookahead carry generator. Four-bit adder

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Combining Block g and p Signals Combining of g and p signals of four blocks of arbitrary widths into the g and p signals for the overall block

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits A Two-Level Carry-Lookahead Adder Building a 64-bit carry-lookahead adder from 16 4-bit adders and 5 lookahead carry generators.

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Ling Adder and Related Designs Consider the carry recurrence and its unrolling by 4 steps: c i = g i–1  c i–1 t i–1 = g i–1  g i–2 t i–1  g i–3 t i–2 t i–1  g i–4 t i–3 t i–2 t i–1  c i–4 t i–4 t i–3 t i–2 t i–1 Ling’s modification: Propagate h i = c i  c i–1 instead of c i h i = g i–1  h i–1 t i–2 = g i–1  g i–2  g i–3 t i–2  g i–4 t i–3 t i–2  h i–4 t i–4 t i–3 t i–2 CLA:5 gatesmax 5 inputs19 gate inputs Ling:4 gatesmax 5 inputs14 gate inputs The advantage of h i over c i is even greater with wired-OR: CLA:4 gatesmax 5 inputs14 gate inputs Ling:3 gatesmax 4 inputs 9 gate inputs Once h i is known, however, the sum is obtained by a slightly more complex expression compared with s i = p i  c i s i = (t i  h i+1 )  h i g i t i–1

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Carry Determination as Prefix Computation

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Formulating the Prefix Computation Problem The problem of carry determination can be formulated as: Given (g 0, p 0 )(g 1, p 1 )... (g k–2, p k–2 )(g k–1, p k–1 ) Find (g [0,0], p [0,0] )(g [0,1], p [0,1] )... (g [0,k–2], p [0,k–2] ) (g [0,k–1], p [0,k–1] ) c 1 c 2... c k–1 c k The desired pairs are found by evaluating all prefixes of (g 0, p 0 ) ¢ (g 1, p 1 ) ¢... ¢ (g k–2, p k–2 ) ¢ (g k–1, p k–1 ) The carry operator ¢ is associative, but not commutative [(g 1, p 1 ) ¢ (g 2, p 2 )] ¢ (g 3, p 3 ) = (g 1, p 1 ) ¢ [(g 2, p 2 ) ¢ (g 3, p 3 )] Prefix sums analogy: Given x 0 x 1 x 2... x k–1 Find x 0 x 0 +x 1 x 0 +x 1 +x 2... x 0 +x x k–1

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits g 0, p 0 g 1, p 1 g 2, p 2 g 3, p 3 g [0,0], p [0,0] = (c 1, --) g [0,1], p [0,1] = (c 2, --) g [0,2], p [0,2] = (c 3, --) g [0,3], p [0,3] = (c 4, --) Example Prefix-Based Carry Network 1 g 0, p 0 g 1, p 1 g 2, p 2 g 3, p 3 g [0,0], p [0,0] = (c 1, --) g [0,1], p [0,1] = (c 2, --) g [0,2], p [0,2] = (c 3, --) g [0,3], p [0,3] = (c 4, --) ¢¢ ¢¢ Four-input prefix sums network Scan order Four-bit Carry lookahead network

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Alternative Parallel Prefix Networks Parallel prefix sums network built of two k/2-input networks and k/2 adders. (Ladner-Fischer)

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Brent-Kung Recursive Construction Parallel prefix sums network built of one k/2-input network and k – 1 adders.

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Brent-Kung Carry Network (8-Bit Adder)

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Brent-Kung Carry Network (16-Bit Adder) Brent-Kung parallel prefix graph for 16 inputs. Reason for latency

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Kogge-Stone Carry Network (16-Bit Adder) Kogge-Stone parallel prefix graph for 16 inputs. log 2 k levels (minimum possible)

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Speed-Cost Tradeoffs in Carry Networks MethodDelayCost Ladner-Fischer?(k/2) log 2 k Kogge-Stone?k log 2 k – k + 1 Brent-Kung?2k – 2 – log 2 k

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Hybrid B-K/K-S Carry Network (16-Bit Adder) A Hybrid Brent-Kung/ Kogge-Stone parallel prefix graph for 16 inputs. Brent-Kung: 6 levels 26 cells Kogge-Stone: 4 levels 49 cells Hybrid: 5 levels 32 cells

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Simple Carry-Skip Adders Converting a 16-bit ripple-carry adder into a simple carry-skip adder with 4-bit skip blocks.

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Another View of Carry-Skip Addition Street/freeway analogy for carry-skip adder.

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Multilevel Carry-Skip Adders One-level carry-skip adder. Example of a two-level carry-skip adder. Two-level carry-skip adder optimized by removing the short-block skip circuits.

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Using Two-Operand Adders Some applications of multioperand addition Multioperand addition problems for multiplication or inner- product computation in dot notation.

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Serial Implementation with One Adder Serial implementation of multi-operand addition with a single 2-operand adder.

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Pipelined Implementation for Higher Throughput Serial multi-operand addition when each adder is a 4-stage pipeline.

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Parallel Implementation as Tree of Adders Adding 7 numbers in a binary tree of adders.  log 2 n  adder levels n – 1 adders

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Carry-Save Adders A ripple-carry adder turns into a carry-save adder if the carries are saved (stored) rather than propagated. Carry-propagate adder (CPA) and carry-save adder (CSA) functions in dot notation. Specifying full- and half- adder blocks, with their inputs and outputs, in dot notation.

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Multioperand Addition Using Carry-Save Adders Tree of carry-save adders reducing seven numbers to two. Carry-propagate adder Serial carry-save addition using a single CSA.

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Example Reduction by a CSA Tree Addition of seven 6-bit numbers in dot notation Bit position  2 = 12 FAs FAs FAs FAs + 1 HA bit adder --Carry-propagate adder Representing a seven-operand addition in tabular form. A full-adder compacts 3 dots into 2 (compression ratio of 1.5) A half-adder rearranges 2 dots (no compression, but still useful)

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Width of Adders in a CSA Tree Adding seven k-bit numbers and the CSA/CPA widths required. Due to the gradual retirement (dropping out) of some of the result bits, CSA widths do not vary much as we go down the tree levels

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Wallace Tree Multiplier

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Wallace Tree Multiplier

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits DADDA Tree Multiplier

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits DADDA Tree Multiplier

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits DADDA Tree Multiplier

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Wallace Tree Multiplier

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Saturating Adders Saturating (saturation) arithmetic: When a result’s magnitude is too large, do not wrap around; rather, provide the most positive or the most negative value that is representable in the number format Designing saturating adders Saturating arithmetic in desirable in many DSP applications Saturation value Overflow 0101 Adder Unsigned (quite easy) Signed (slightly harder) Example – In 8-bit 2’s-complement format, we have:  18 (wraparound); sat 26  127 (saturating)

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Readings:  Main reference for the above slides:  Chapters 5,6,7,& 8, B. Parhami, Computer Ar ithmetic: Algorithms and Hardware Design, O xford University Press, 2000.