A Direct Conversion CMOS Transceiver for IEEE802.11a WLANs Pengfei Zhang RF Micro Devices, San Jose, California I’ll present A direct conversion CMOS transceiver designed for wireless local area network applications. 3/18/2004

Transceiver Architecture Frequency Planning Circuit Design Outline Introduction Transceiver Architecture Frequency Planning Circuit Design Measured Results Conclusion This is the outline of my talk. After a brief introduction, I will discuss the radio architecture selection, frequency planning and circuit design details. I will then present the measured results before concluding the talk. 3/18/2004

Wireless Connectivity Cellular WLAN This is the outline of my talk. After a brief introduction, I will discuss the radio architecture selection, frequency planning and circuit design details. I will then present the measured results before concluding the talk. GPS Bluetooth™ 3/18/2004

WLAN - Mobility vs. Bit Rate Outdoor Stationary Walk Vehicle Indoor Stationary/ Desktop WLAN (IEEE 802.11a/b/g) W-CDMA/ EDGE Mobility Bluetooth Zigbee (IEEE 802.15) LAN 0.1 1 10 100 Mb/s Bit Rate 3/18/2004

WLAN - Cost vs. Bit Rate $ W-CDMA/ EDGE High Medium W-CDMA/ EDGE User Cost / bit HIPERLAN/2 Low WLAN (IEEE 802.11a/b/g) Bluetooth Zigbee (IEEE 802.15) Very Low LAN LAN 0,1 1 10 100 Mb/s Bit Rate 3/18/2004

Two-Chip WLAN System 3/18/2004 The transceiver chip is designed for in-door application in the UNII band from 5.15 to 5.35 GHz specified by IEEE802.11a standard. The 11a standard requires a data rate-dependent minimum receive sensitivity at –65 dBm for 54 Mb/s and –82 dBm for 6 Mb/s. 11a standard further requires a maximum transmit constellation error at –25 dB for 64 QAM modulated OFDM signal, where as the output power can not exceed 16dBm. Our design goal is to exceed the 11a performance requirement while making major effort in achieving low cost and low power consumption. Ref. J. Bohac, Flexible chipset arms 802.11a/b/g WLANs, Microwaves and RF, May 2003 3/18/2004

Design Goals The transceiver chip is designed for in-door application in the UNII band from 5.15 to 5.35 GHz specified by IEEE802.11a standard. The 11a standard requires a data rate-dependent minimum receive sensitivity at –65 dBm for 54 Mb/s and –82 dBm for 6 Mb/s. 11a standard further requires a maximum transmit constellation error at –25 dB for 64 QAM modulated OFDM signal, where as the output power can not exceed 16dBm. Our design goal is to exceed the 11a performance requirement while making major effort in achieving low cost and low power consumption. Design Goals: To exceed standard performance requirement, achieve low power consumption and low cost 3/18/2004

Direct Conversion vs. Low-IF Conversion (I) This effort starts with the radio architecture selection. We first make an observation that the superhetrodyne architecture requires SAW filters and is not a preferred solution. We then compare direct conversion with low IF conversion. We realized that direct conversion suffers impairments of flicker noise, dc offset, even order distortion, lo pulling and lo leakage, while low-if conversion is less susceptible to flicker noise and dc offset. However, low-if conversion does also suffer impairments of even order distortion, lo pulling and lo leakage. 3/18/2004

Direct Conversion vs. Low-IF Conversion (II) Image Response Direct conversion: No Image Low-IF conversion: Analog image rejection – I/Q matching, Circuit complexity DSP image rejection – large ADC dynamic range required ADC Sampling Rate f flow-IF conversion= 2*fdirect conversion Baseband Filters Direct conversion: BW ~ 10 MHz Low-IF conversion: BW ~ 20 MHz More Power! We further compare direct conversion with low-if conversion with regard to the I/q matching requirement. In direct conversion, the ever-existing I/q mismatch from the radio can be measured and compensated in baseband DSP. In low-if conversion, on the other hand, the image response due to I/q mismatch corrupts the desired signal and can not be removed in the digital domain. Moreover, the signal bandwidth in low-if conversion is twice that in direct conversion, therefore requires to double the ADC sampling rate, results in higher power consumption. Finally, the double signal bandwidth in low-if conversion mandates to double the baseband filter bandwidth, which further increases design complexity and power consumption. We therefore decided to take on the technical challenges of direct conversion for its potential in low cost and low power. 3/18/2004

Transceiver Architecture AGC LNA LPF To ADC LO-0o RF IN To ADC LPF Receiver LO-90o AGC 0o 5.25GHz 90o Transmitter LPF Synthesizer RF OUT The transceiver is integrated on a single chip. It contains a direct conversion RX, where the received RF signal is first amplified by a single ended LNA, then directly down converted to baseband signals through a pair of mixers. The baseband section consists of an AGC stage and a channel selection LPF. The transceiver further contains a direct conversion transmitter, where the baseband signal from the DAC is low-pass filtered and upconverted to RF thru a SSB DB mixer. Diff to single-ended conversion is performed on chip, so that users don’t have to design a balun. Programmable output power is achieved with the PA driver design. The integrated frequency synthesizer employs a unique frequency planning to avoid LO pulling, which I will discuss in more detail. From DAC LO-0o LO-90o From DAC PAD LPF 3/18/2004

Example of Frequency Planning (Ref.[2]) cos(2wt/3) cos(wt/3) cos(wt)+cos(wt/3) ¸ 2 sin(wt)+sin(wt/3) sin(wt/3) VCO Divider Mixer Unwanted Sideband 2w/3 w/3 w/3 w In ref. [2], a LO generation scheme consists of VCO operating at two thirds of the LO frequency and a divide-by-2 circuit producing quadrature outputs at one third LO frequency. Two mixers subsequently mixing the VCO signal and the divide-by-2 signal generate both in-phase and quadrature LO signals. As the VCO operates at two third of the LO frequency, this scheme can effectively avoid pulling and reduce LO-RF interaction. However, the generated LO signal has strong sideband at one third of LO frequency. In our case, this is roughly 1.8GHz, a highly populated frequency band where high power transmitter exists. It therefore generates image problem in receive mode and degrades efficiency in transmit mode. This also makes it more challenging to meet FCC spur requirement. Avoid pulling, reduce LO-RF interaction However, unwanted sideband at w/3: RX: image in highly populated band (1.8GHz) TX: degrades efficiency; FCC requirement 3/18/2004

Proposed Frequency Planning cos(2wt/3) cos(wt) cos(wt/3) ¸ 2 5.25GHz 1.75GHz 3.5GHz sin(wt/3) sin(2wt/3) sin(wt) VCO Buffer Divider SSB Mixer LO Driver In this work, we used a quadrature VCO based on cross-couple LC resonators to generate both in-phase and quardrature signals at 2/3 LO freq. We further used single sideband mixers in LO generation, which suppresses the unwanted side band. The generated LO signal has a cleaner frequency content at the LO frequency, minimizing the adverse effect of the unwanted sideband. 2w/3 w/3 w/3 w Quadrature VCO: cross coupled LC resonators SSB Mixer: suppress unwanted sideband 3/18/2004

IM2 of Multi-carrier We now look at the RX architecture in more detail. In the RX chain, a single ended cascode LNA is used, which can also be programmed to low gain setting. Direct down conversion is performed by the v/I and mixer stage. A notch filter provides partial channel selection filtering to relax linearity requirement of the BB stages. Baseband section consists of an AGC stage and a channel selection low pass filter, which is designed to have a 7th order Chebyshev response with a nominal cut-off freq of 8.7MHz and a stop band attenuation of 60dB. As DC is more susceptible to 2nd order nonlinearity, AC coupling is used throughout the RF front-end and baseband section blocks are fully differential, so as to achieve high IP2. DC offset compensation is achieved with two 7b DAC’s. Since the offset changes with the LNA gain setting, a LUT is incorporated and pre-calibrated compensation values can be selected based on gain control. Ref. K. Cai, P. Zhang, Microwave Journal, Feb. 2004 3/18/2004

ADS Simulation of IM2 Impairment Ref. K. Cai, P. Zhang, Microwave Journal, Feb. 2004 3/18/2004

Receiver Architecture Notch Filter AGC LPF To ADC DAC LNA V/I Converter LO-0o LO-90o RF IN From baseband LUT I Q We now look at the RX architecture in more detail. In the RX chain, a single ended cascode LNA is used, which can also be programmed to low gain setting. Direct down conversion is performed by the v/I and mixer stage. A notch filter provides partial channel selection filtering to relax linearity requirement of the BB stages. Baseband section consists of an AGC stage and a channel selection low pass filter, which is designed to have a 7th order Chebyshev response with a nominal cut-off freq of 8.7MHz and a stop band attenuation of 60dB. As DC is more susceptible to 2nd order nonlinearity, AC coupling is used throughout the RF front-end and baseband section blocks are fully differential, so as to achieve high IP2. DC offset compensation is achieved with two 7b DAC’s. Since the offset changes with the LNA gain setting, a LUT is incorporated and pre-calibrated compensation values can be selected based on gain control. 7th order Chebyshev “leapfrog” LPF Improved IP2: AC coupled RF, fully diff baseband DC offset compensation: 7b DAC; Look-up-table 3/18/2004

Mixer Design R2 R1 R2 R1 L1 Out+ Out- Out+ Out- LO+ LO- LO+ LO- M2 M3 M2 M3 M1 M1 RF C1 RF C1 I1 I2 I1 C2 C2 Conventional single balanced mixer: tradeoff between 1/f noise and linearity As the cascode LNA design is straightforward, I would like to further discuss the mixer design. Mixer is the most critical stage in combating the flicker noise. In a conventional single balanced mixer, one faces a difficult tradeoff in choosing the proper biasing of I1. The switching quad M2, M3 exhibits lower flicker noise if I1 can be reduced, while the v/I converter M1 requires high biasing current to achieve a decent conversion gain and good linearity. In this work, a two-stage mixer is used where the V/I converter and the switching quad biasing currents can be independently optimized. Simulation shows that the two-stage mixer achieves 10dB better iip3 and 5dB better NF while maintaining the same conversion gain. Note also the V/I output is ac coupled to the switching quad, further improves the 2nd order intercept point. We further implemented digital gain control in the mixer stage, by replacing the mixer load resistor with an R-2R ladder. Two-stage mixer: Independent biasing I2: linearity, I1: 1/f noise 3/18/2004

Digital Gain Control: R-2R Ladder Sj1 Sj3 Sj4 Sj5 Sj2 Sj0 S(j-1)0 I1 VOUT R 2R S00 Sn0 Sj0 S10 Mixer Current I1 VDD When Sjk=1, DGjk=-6*j+20LOG(1+k/6) (dB) The mixer load resistor is designed as a 10 section R-2R ladder. By switching the mixer output current to various node in the R-2R network, the output voltage signal (VOUT) varies in the power of 2, realizing 6dB/step gain control. Each R in the network can be further split into 6 equal parts and achieve finer gain variation at roughly 1dB/step, as indicated in the formula and the transfer curve. Note that the R-2R ladder guarantees monotonic gain control. It is highly linear, settles fast and maintains constant output impedance. Mixer resistive load: 10-section R-2R ladder Monotonic, linear, fast settling and Constant Rout 3/18/2004

Notch Filter: Active-LC Trap Mixer Vout VDD C1 I1 R1 M5 C2 The RX chain further contains a notch filter to provide partial channel selection. With proper biasing I1, M5 together with R1 and C2 presents an inductive impedance in series with C1, thus generates a 14dB notch at alternate adjacent channel of 40MHz when coupled to the output of the mixer. The notch filter significantly relaxes the linearity requirement of the baseband stages. Measurement shows that it improves the RX out-of-channel IIP3 by 7dB. The notch filter takes minimal silicon area and contribute negligible flicker noise to the signal path. Partial channel selection filter to relax linearity requirement of baseband stages Synthesized L takes minimal silicon area Large low frequency impedance of C1 minimize flicker noise contribution from M5 3/18/2004

AGC For an input signal ramping in power, the RX gain is adjusted to maintain a constant output signal power level. Although the RX noise figure increases in low gain settings, the output SNR remains higher than 34 dB in the entire dynamic range. 3/18/2004

RX LPF Frequency Response 3/18/2004

Transmitter Architecture Offset Control From DAC LPF I LO-0o LO-90o From DAC LPF PA Driver Power Amp In the transmitter chain, the LPF is designed to have a 4th order butterworth response with a nominal corner freq at 12MHz. After reconstruction filtering, the modulated signal is upconverted by a SSB DB mixer. The diff signal is subsequently converted to single-ended and further amplified by a power amplifier driver. Off-chip power amplifier is to be used for the overall system power saving. Q Offset Control LPF: 4th order Butterworth Off-chip PA used for system power saving 3/18/2004

TX LPF Frequency Response 3/18/2004

Transmitter RF Front-end Vdd RFout L1 L2 Vbbi M0 C0 M3 C3 R0 LOi D0 M1 LOq M4 C1 R1 D1 Vbbq D/S Converter M2 C2 We now look at the tx circuit design in more detail. The upconversion is performed by SSB DB mixer. In a direct conversion tx, lo leakage resides at the center of the rf signal freq band. It is not possible to remove it with rf filter. Although lo leakage can be due to direct coupling or dc offset, it can be compensated by applying a baseband dc offset regardless of its origin. DC offset tuning is introduced to the DB mixers to suppress LO leakage. Suppression of better than 38dBc is achieved without affecting the linearity or dynamic range of the TX, more than 20dB better than 11a requirement. The diff to single-ended conversion is performed on chip, so that users don’t have to provide off-chip balun. The D/S converter consists of a capacitively degenerated common source amplifier M3, whose gate senses the positive node of the diff signal in voltage domain and combines with the negative node in current domain at the drain. The D/S converter shares the load inductors of the upconversion mixers, consequently saves area and power consumption. (note: pls make correction in the digest by adding C3 to the schematic) The PAD is designed as binary weighted parallel fingers of M0, M1 and M2, so as to achieve programmable output power. offset tuning D2 R2 LO leakage: Mixer DC offset tuning D/S converter: No need of off-chip balun Programmable Pout: Binary weighted PA driver 3/18/2004

Frequency Synthesizer Automatic VCO band selection Accumulation mode NMOS varactors Off-chip 40 MHz XTAL and loop filter (~200 KHz) 3.5GHz ¸ M PFD ¸ N VH decision VL Band Selection The freq synthesizer is designed as an integer-N phase locked loop. The freq divider is implemented using a dual modulus 8/9 prescaler and a 13b pulse swallow counter. Freq synthesizer further contains a phase-freq-detector and a high performance charge pump. With a power supply voltage of 1.8 volts, the vco gain tends to be quite high in order to cover the required freq range. A high vco gain results in high sensitivity to the noise of vco tuning voltage, which increases the spur level and degrades phase noise. In this work, the required freq range is divided into nine bands, each about 60MHz wide with 30MHz overlap between adjacent bands. An automatic band selection scheme is implemented by connecting unit caps to the VCO core while monitoring the Varactor tuning voltage. Therefore achieve sufficient freq tuning range while maintaining a moderate VCO gain. Within each band, continuous freq tuning is achieved by using accumulation mode NMOS varactors. Using a ref clock at 40MHz, off-chip loop filter with bandwidth of roughly 200KHz is found to be optimal for phase noise performance. XTAL timer 3/18/2004

VCO Frequency Bands 3/18/2004

Die Photo 0.18 mm 1P-6M CMOS with MIM-C 3/18/2004 The transceiver chip is fabricated in CMOS process with feature size of 0.18um, single poly, 6 layers of metal and options of MIM-C and high sheet rho poly resistors. The total die area is less than 13 mm2. It is packaged in a 64-pin micro-lead frame with back side central grd plate. 0.18 mm 1P-6M CMOS with MIM-C 3/18/2004

Receiver Gain & Noise Figure RX gain and noise figure have been measured as a function of baseband output frequency with a RBW of 50KHz. The RX provides 58dB voltage gain with a spot noise figure of 6.8dB. Flicker noise effect manifests itself at and below 1MHz. According to 11a standard, the 1st carrier of the OFDM signal starts at 150KHz, where the noise figure is about 8dB, still 2dB better than the 11a noise figure assumption of 10dB. The xfer curve also shows the LPF corner freq at 8.7MHz. 3/18/2004

Receiver Sensitivity 3/18/2004 The received packet error rate of the rx is measured with PSDU of 1000 bytes as indicated in the ieee standard. The number of frames can be used is limited by the measurement system memory. The sensitivity level is defined by the 11a standard as the minimum input power when PER reaches 10%. We therefore have a sensitivity of –91dBm at 6 Mb/s and –74dBm at 54Mb/s, both 9dB better than 11a requirement. (Incidentally, this measurement shows better results than quoted in the digest, as we improved further the board design and reduced the input loss). 3/18/2004

TX Transmit Spectrum 3/18/2004 The transmitted spectrum of a 64QAM OFDM signal is plotted against the spectrum mask defined by ieee standard. With a total output power of 16.2dBm, the output spectrum is well below the spectrum mask, indicating a good linearity margin. Note that the transceiver chip delivers roughly –5dBm of total power in this case, the rest of RF gain is made up by an external PA. 3/18/2004

TX Transmit Spectrum 3/18/2004 The transmitted spectrum of a 64QAM OFDM signal is plotted against the spectrum mask defined by ieee standard. With a total output power of 16.2dBm, the output spectrum is well below the spectrum mask, indicating a good linearity margin. Note that the transceiver chip delivers roughly –5dBm of total power in this case, the rest of RF gain is made up by an external PA. 3/18/2004

PAPR in OFDM System 52 Subcarriers: 17dB (=10*log52) PAPR 50 100 150 50 100 150 200 250 300 10 20 30 40 60 70 3/18/2004

Peak Power Probability Large peaks do not occur very often (Gaussian distribution) 4 5 6 7 8 9 10 11 12 13 14 2000 4000 6000 8000 10000 12000 PAPR(dB) 3/18/2004

TX Transmit Spectrum 3/18/2004 The transmitted spectrum of a 64QAM OFDM signal is plotted against the spectrum mask defined by ieee standard. With a total output power of 16.2dBm, the output spectrum is well below the spectrum mask, indicating a good linearity margin. Note that the transceiver chip delivers roughly –5dBm of total power in this case, the rest of RF gain is made up by an external PA. 3/18/2004

Transmit Constellation Output power: 16.2dBm 64QAM, 54Mb/s Average EVM: 3.41%, -29.3dB This is the transmit constellation of the same 64QAM OFDM signal. The error vector magnitude is found to be less than –29dB, well below the standard requirement of –25dB. Indicating sufficient linearity and phase noise performance. 3/18/2004

LO Spectrum The LO spectrum is measured at both the divided by 2 output and the tx output with RBW of 10KHz and a VBW of 500Hz. The 13.3MHz spur is originated from the ref clock, and is found to be 66dB lower than the main tone, sufficient to meet both the ieee spectrum mask spec and the FCC regulation. 3/18/2004

LO Phase Noise The open loop VCO phase noise has been characterized at the divided by 2 output. Center around 1.75GHz, the single side band phase noise is roughly –120dBc/Hz at an offset freq of 1MHz. The closed loop phase noise is measured at the TX output with the center frequency at 5.25GHz. Integrated from 10KHz to 10MHz, the total phase error is less than 1.5 degree. 3/18/2004

RX Switch On Settling Time It is required by the ieee standard that the RX-TX turn around time to be less than 2 usec. We measured the RX switching on time by applying a fixed CW tone at the RX input and plot the power on clock signal together with the RX output signal. The switch on settling time is measured to be less than 1.6usec. 3/18/2004

TX Switch On Settling Time Similar test has been performed on the transmitter where a fixed baseband complex signal is applied at the TX input. An always on RX is coupled in series with the TX and the down converted signal at the RX output is plotted together with the power on clock applied to the TX. Note that the 1.6us delay includes about 0.5us propagation delay in the always-on RX. TX switch on settling time nevertheless meets standard requirement. 3/18/2004

Performance Summary *External PA used 3/18/2004 In summary, the transceiver chip exhibits a sensitivity level of –91dBm at 6Mb/s and –74dBm at 54Mb/s, both 9dB better than the standard requirement. With an external PA, the transmitter delivers 16.2dBm of OFDM power to the antenna with a relative constellation RMS error less than –29dB while achieving LO rejection of 38dBc, both exceed the standard requirement. With a power supply at 1.8v, the power cons in the RX mode is 171mw and 135mW in the TX mode. The chip area is less than 13 mm2. *External PA used 3/18/2004

Conclusion CMOS Direct-Conversion Transceiver with integrated VCO and frequency synthesizer fully compliant with IEEE 802.11a standard Exceeding standard performance requirement with low power consumption and small die area In conclusion, We realized in CMOS process a direct-conversion transceiver chip with integrated VCO and freq synthesizer, exceeding all major standard performance requirement while achieved low power and small die area. 3/18/2004