1 Quarterly Technical Report 1 for Pittsburgh Digital Greenhouse Kyusun Choi The Pennsylvania State University Computer Science and Engineering Department.

Slides:

Advertisements

Similar presentations

1 500cm 83cm 248cm TPC DETECTOR 88us 1MIP = 4.8 fC = 3 x10 4 e Dynamic : 30 MIP S / N = 30:1 1MIP = 4.8 fC = 3 x10 4 e Dynamic : 30 MIP S / N = 30:1 LATERAL.

Advertisements

Mixed Signal Chip Design Lab CMOS Analog Addition/Subtraction Jaehyun Lim, Kyusun Choi Department of Computer Science and Engineering The Pennsylvania.

1 A New Successive Approximation Architecture for Low-Power Low-Cost A/D Converter IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.38, NO.1, JANUARY 2003 Chi-sheng.

Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania ECE VLSI Circuit Design Lecture 5 - Hierarchical.

Design, Verification, and Test of True Single-Phase Adiabatic Multiplier Suhwan Kim IBM Research Division T. J. Watson Research Center, Yorktown Heights.

Analog-to-Digital Converters

Characterization of a CMOS cell library for low-voltage operation

S. Reda EN1600 SP’08 Design and Implementation of VLSI Systems (EN1600) Lecture 24: Computer-Aided Design using Tanner Tools Prof. Sherief Reda Division.

A Low-Power 4-b 2.5 Gsample/s Pipelined Flash Analog-to-Digital Converter Using Differential Comparator and DCVSPG Encoder Shailesh Radhakrishnan, Mingzhen.

14-5 January 2006 Luciano Musa / CERN – PH / ED General Purpose Charge Readout Chip Nikhef, 4-5 January 2006 Outline  Motivations and specifications 

Electrical Engineering Student Senior Capstone Project: A MOSIS FFT Processor Chip-Set Peter M. Osterberg & Aziz S. Inan Donald P. Shiley School of Engineering.

I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

Slide: 1International Conference on Electronics, Circuits, and Systems 2010 Department of Electrical and Computer Engineering University of New Mexico.

A 30-GS/sec Track and Hold Amplifier in 0.13-µm CMOS Technology

Second generation Front-end chip for H-Cal SiPM readout : SPIROC DESY Hamburg – le 13 février 2007 M. Bouchel, F. Dulucq, J. Fleury, C. de La Taille, G.

CS-EE 481 Spring University of Portland School of Engineering Project Golden Mantle CMOS 8-Bit Analog-to-Digital Converter Team T Travis Tompkins.

R. Kass US LC Conference 1 Design and Fabrication of a Radiation-Hard 500-MHz Digitizer Using Deep Submicron Technology R. Kass The Ohio State University.

1 Hall D Drift Chamber ElectronicsFJ Barbosa Drift Chamber Review6-8 March 2007 Electronics for CDC and FDC Hall D 1.Motivation 2.ASIC Development 3.Preamp.

1 5. Application Examples 5.1. Programmable compensation for analog circuits (Optimal tuning) 5.2. Programmable delays in high-speed digital circuits (Clock.

Interconnect Focus Center e¯e¯ e¯e¯ e¯e¯ e¯e¯ IWSM 2001Sam, Chandrakasan, and Boning – MIT Variation Issues in On-Chip Optical Clock Distribution S. L.

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering Project Golden Eagle CMOS Fast Fourier Transform Processor Team.

Mixed Signal Chip LAB.Kyoung Tae Kang Dynamic Offset Cancellation Technique KyoungTae Kang, Kyusun Choi CSE598A/EE597G Spring 2006.

QIE10 Issues Tom Zimmerman Fermilab Oct. 28,

Resistance to Frequency Converter Amol Mupid Andrew Ricketts.

Mixed Signal Chip Design Lab Cubic Function Generator Design Boram Lee, Jaehyun Lim Department of Computer Science and Engineering The Pennsylvania State.

Progress on STS CSA chip development E. Atkin Department of Electronics, MEPhI A.Voronin SINP, MSU.

Development of an ASIC for reading out CCDS at the vertex detector of the International Linear Collider Presenter: Peter Murray ASIC Design Group Science.

Mixed Signal Chip Design Lab Cubic Function Generator Design Boram Lee, Jaehyun Lim Department of Computer Science and Engineering The Pennsylvania State.

Mixed Signal Chip Design Lab Operational Amplifier Configurations Jaehyun Lim, Kyusun Choi Department of Computer Science and Engineering The Pennsylvania.

Background: VLSI Courses at Lafayette  ECE VLSI Circuit Design  Original form: “tall thin designer”  VLSI Processing  CMOS Transistor Characteristics.

Preliminary Design of FONT4 Digital ILC Feedback System Hamid Dabiri khah Queen Mary, University of London 30/05/2005.

New Power Saving Design Method for CMOS Flash ADC Institute of Computer, Communication and Control, Circuits and Systems, July 2004 IEEE 班級：積體碩一姓名：黃順和.

L.ROYER – TWEPP Oxford – Sept The chip Signal processing for High Granularity Calorimeter (Si-W ILC) L.Royer, J.Bonnard, S.Manen, X.Soumpholphakdy.

Resistance to Frequency Converter Amol Mupid Andrew Ricketts.

Mixed Signal Chip Design Lab Cubic Function Generator Design Boram Lee, Jaehyun Lim Department of Computer Science and Engineering The Pennsylvania State.

High Speed Analog to Digital Converter

ABSTRACT The purpose of this project is to develop an amplifier for Teradyne Corporation. The amplifier will take the input signal and amplify it without.

Project submitted By RAMANA K VINJAMURI VLSI DESIGN ECE 8460 Spring 2003.

Valerio Re, Massimo Manghisoni Università di Bergamo and INFN, Pavia, Italy Jim Hoff, Abderrezak Mekkaoui, Raymond Yarema Fermi National Accelerator Laboratory.

Fall CS-EE 480 University of Portland School of Engineering Project Meadowlark CMOS Programmable Digital Low-Pass Filter Jennifer Galaway Jennifer.

Technical Report High Speed CMOS A/D Converter Circuit for Radio Frequency Signal Kyusun Choi Computer Science and Engineering Department The Pennsylvania.

1 Status Report on ADC LPC Clermont-Ferrand Laurent ROYER, Samuel MANEN.

Pipelined ADC We propose two variants: low power and reliability optimized A. Gumenyuk, V. Shunkov, Y. Bocharov, A. Simakov.

Analog to Digital Converters

Low Power, High-Throughput AD Converters

1 The Link-On-Chip (LOC) Project at SMU 1.Overview. 2.Status 3.Current work on LOCs6. 4.Plan and summary Jingbo Ye Department of Physics SMU Dallas, Texas.

EDA (Circuits) Overview Paul Hasler. Extent of Circuits (Analog/Digital) Analog ~ 20% of IC market since 1970 Hearing aids Automotive Biomedical Digital.

Fermilab Silicon Strip Readout Chip for BTEV

1 Quarterly Technical Report II for Pittsburgh Digital Greenhouse Kyusun Choi The Pennsylvania State University Computer Science and Engineering Department.

Low Power, High-Throughput AD Converters

S. Bota – Calorimeter Electronics overview - July 2002 Status of SPD electronics Very Front End Review of ASIC runs What’s new: RUN 4 and 5 Next Actions.

CS-EE 481 Spring University of Portland School of Engineering Project Golden Mantle CMOS 8-Bit Analog-to-Digital Converter Team T Travis Tompkins.

1 19 th January 2009 M. Mager - L. Musa Charge Readout Chip Development & System Level Considerations.

Technical Report 4 for Pittsburgh Digital Greenhouse High Speed CMOS A/D Converter Circuit for Radio Frequency Signal Kyusun Choi Computer Science and.

Characterizing Processors for Energy and Performance Management Harshit Goyal and Vishwani D. Agrawal Department of Electrical and Computer Engineering,

Low Power, High-Throughput AD Converters

A General Purpose Charge Readout Chip for TPC Applications

DCD – Measurements and Plans

Hugo França-Santos - CERN

Software Defined Radio Transceiver Implementation

Ultra-Low-Voltage UWB Baseband Processor

1 Gbit/s Serial Link 1 Gbit/s Data Link Using Multi Level Signalling

Design for Simple Spiking Neuron Model

Combinational Circuits

Quarterly Technical Report III for Pittsburgh Digital Greenhouse

Combinational Circuits

Project Meadowlark CMOS Programmable Digital Low-Pass Filter

A 12 bit 50 MS/s Dual Channel Time Domain Two Step ADC

A 12 bit 50 MS/s Dual Channel Time Domain Two Step ADC

Presentation transcript:

1 Quarterly Technical Report 1 for Pittsburgh Digital Greenhouse Kyusun Choi The Pennsylvania State University Computer Science and Engineering Department High Speed CMOS A/D Converter Circuit for Radio Frequency Signal

2 Project goals for this quater 1.Design a 6 and 8 bit TIQ based flash ADC circuits and CMOS layouts 2.Design the first prototype chip: 6 and 8 bit flash ADC 3. Chip fabrication submission

3 Accomplished project milestones for this quarter 1.Designed 6, 8, and 9 bit TIQ based ADC circuits and CMOS layouts in 0.25  m 2.Designed the first prototype chip: 6, 8, and 9 bit flash ADC 3.Fabrication submission preparation 4.Chip fabrication submission: - Submission date: 4/2/ Vendor: MOSIS with TSMC 0.25  m foundry - Expected prototype chip delivery date: 7/16/2001

4 1.Systematic Variation Approach - Systematic Parameter Variation (SPV) 2.CAD Tools - MAX for layout - SUE for schematic capture - HSPICE for circuit simulation - Custom designed a set of C programs 3. Experiment base, Spice Model Base Design Method

5 Chip Block Diagram Chip Layout Design (1)

6 Dimension - ADCs - Chip size (2580um * 2580um) Chip Layout Design (2) ADCsSize (W*H) umArea (mm 2 ) 6bit high speed * bit low power * bit high speed * bit low power * bit high speed * bit low power *

7 Layout - 6bit (0.24 um) Chip Layout Design (3)

8 Layout - 6bit (1.00 um) Chip Layout Design (4)

9 Layout - 8bit (0.24 um) Chip Layout Design (5)

10 Layout - 8bit (0.50 um) Chip Layout Design (6)

11 Layout - 9bit (0.50 um) Chip Layout Design (7)

12 Layout - 9bit (1.00 um) Chip Layout Design (8)

13 Layout - Pad Chip Layout Design (9)

14 Layout - Chip Chip Layout Design (10)

15 Simulation Results (1) ADCs Max. Speed (MSPS) Max. Current (mA) Avg. Power (mW) Max. Power (mW) 6bit (0.24um) bit (1.00um) bit (0.24um) bit (0.50um) bit (0.50um) bit (1.00um) pad delay : ns

16 Simulation Results (2) - 6bit (0.24um)

17 Simulation Results (3) - 6bit (1.00um)

18 Simulation Results (4) - 8bit (0.24um)

19 Simulation Results (5) - 8bit (0.50um)

20 Simulation Results (6) - 9bit (0.50um)

21 Simulation Results (7) - 9bit (1.00um)

22 1.High Speed 2.Relatively small area 3. Relatively low-power Features of the TIQ based ADC

23 1. Dynamic fine-tuning 2. Supply voltage variation compensation 3. Temperature variation compensation 4. Process variation compensation 5. Lower power 6. FIFO design for on-chip high-speed data acquisition Issues to Be Addressed in Future

24 2 GSPS with 0.18um CMOS Custom layout CAD tool 10bit and 12bit ADC Low power Dynamic calibration Offset Gain Temperature Power supply voltage Process parameter variation Innovation Challenges

25 High speed ADC for RF ADC core - 6, 8 and 9 bit design first prototype chip (silicon test) 0.25  m MOSIS (tsmc) process CMOS digital logic technology Future ready Dynamic calibration Summary