Lecture 2.0 Thermodynamics in Chip Processing Terry Ring

Field Effect Transistor (FET)

Gate Oxide Capacitor connecting Gate to center of npn or pnp heterojunction Capacitance –Area –Thickness –Dielectric constant of oxide Dictates the Speed of the Switch

Gate Oxide Capacitance C=  o A/d  =C/C o  =1+  e  e = electric susceptibility

Field Effect Transistor (FET)

Silicon Oxidation Thermodynamics (yes/no? How Far? Heat/cool) –Furnace at T=850C –Pure Oxygen Si + O 2  SiO 2 Kinetics (how fast) –BL-Mass Transfer J=K g (C A -0) –SS-Diffusion J=D O-SiO2 (dC/dx) –Heat Transfer BL, q=h(T 1 -T) Solid, q=k SiO2 (dT/dx) –J=q/  H rxn

Thermodynamics of Reactions Thermodynamics Can Tell you Three Things –Is reaction spontaneous Gibbs Free Energy, ΔG rxn (T) –  Grxn<0, Spontaneous –  Grxn>0, Non-Spontaneous –What are Equilibrium Ratios? ΔG rxn (T)= - RT ln(K eq ) –Does Reaction create heat? Heat of Reaction, ΔH rxn (T) –Exothermic, ΔH rxn (T)<0, get hot! –Endothermic, ΔH rxn (T)>0

Reaction to Make SiO 2 Si (s) + O 2 (g)   SiO 2 (s) –Done in Vacuum Furnace. Does the Reaction Go? – P o 2 =0.001 atm – T= 600 C

Gibbs Free Energy Si (s) + O 2 (g)   SiO 2 (s) ΔG rxn (T)=G SiO 2 (T) - G Si (T) - G O 2 (T) = - RT ln(K eq ) -ΔG o rxn (T)=G SiO 2 (T) - G Si (T) - G O 2 (T) K eq =Xo 2= Po 2/P Tot If ΔG rxn (T)=0, then ΔG o rxn (T) = - RT ln(Po 2 ) G SiO 2 (T) = ΔH SiO2 (T) -TΔS o SiO2 ΔH SiO2 (T) =H o f-SiO 2 + To ∫ T C p-SiO 2 (T) dT G Si (T) = ΔH Si (T) -TΔS o Si ΔH Si (T) =H o f-Si + To ∫ T C p-Si (T) dT  G rxn <0, Spontaneous webbook.nist.gov/chemistry/

P o 2 = atm T = 600 C ΔG rxn (T)= ΔG o rxn (T) - RTln(Po 2 ) -180 kcal/mole-(-10kcal/mole) = -170 kcal/mole Spontaneous!

Want to Create O 2 with wet H 2 H 2 O(g)   H 2 (g) + ½ O 2 (g) Equilibium ΔG rxn (T)= - RT ln(K eq ) K eq = (X H 2 √X o 2 )/X H 2 O ΔG rxn (T)= ΔG H 2 (T)+1/2 ΔG o 2 (T)- ΔG H 2 O (T)

At T = 600 C What H 2 /H 2 O Ratio?

Want to Create O 2 with CO/CO 2 ratio 2CO 2 (g)   2CO(g) + O 2 (g) Equilibium ΔG rxn (T)= - RT ln(K eq ) K eq = (X CO 2 X o 2 )/X CO 2 2 ΔG rxn (T)= 2ΔG CO (T)+ΔG o 2 (T) - 2ΔG CO 2 (T)

At T = 600 C What CO/CO 2 Ratio?

What Memory Chip Really Looks Like

Metalization Transistor Contacts –Base –Emitter –Gate Metal Deposition –Chemical Vapor Deposition

CVD of Poly Si – Gate conductor SiH 4  Si (s) + 2 H 2 –620C, vacuum –N 2 Carrier gas with SiH 4 and dopant precursor Stack of wafer into furnace –Higher temperature at exit to compensate for gas conversion losses Add gases Stop after layer is thick enough

CVD Reactor Wafers in Carriage (Quartz) Gasses enter Pumped out via vacuum system Plug Flow Reactor Vacuum

CVD of W – Metal plugs 3H 2 +WF 6  W (s) + 6HF –T>800C, vacuum –He carrier gas with WF 6 –Side Reactions at lower temperatures Oxide etching reactions 2H 2 +2WF 6 +3SiO 2  3SiF 4 + 2WO 2 + 2H 2 O SiO 2 + 4HF  2H 2 O +SiF 4 Stack of wafer into furnace Add gases Stop after layer is thick enough

Chemical Equilibrium

DRAM Memory Cell 1 Bit Capacitor Gate or Row Line Column Line N P N SiO 2 Si Wafer

CVD of SiO 2 – Dielectric Si(0C 2 H 5 ) 4 +7O 2  SiO 2 (s)+ 10 H 2 + 8CO 2 –400C, vacuum –He carrier gas with vaporized(or atomized) Si(0C 2 H 5 ) 4 and O 2 and B(CH 3 ) 3 and/or P(CH 3 ) 3 dopants for BSG and BPSG Stack of wafer into furnace –Higher temperature at exit to compensate for gas conversion losses Add gases Stop after layer is thick enough

CVD of Si 3 N 4 - Implantation mask 3 SiH 2 Cl NH 3  Si 3 N 4 (s)+ 6 HCl + 6 H 2 –780C, vacuum –Carrier gas with NH 3 / SiH 2 Cl 2 >>1 Stack of wafer into furnace –Higher temperature at exit to compensate for gas conversion losses Add gases Stop after layer is thick enough