Suggestions for FPGA Design Presentation Dr. Rod Barto NASA/Office of Logic Design rbarto@klabs.org

Suggestions for FPGA Design Presentation Goals Detailed design review and worst case analysis are the best tools for ensuring mission success. The goal here is not to make more work for the designer, but to: Enhance efficiency of reviews Make proof of design more clear Make design more transferable Improve design quality Suggestions for FPGA Design Presentation

Steps to preparing for design review Modularize your design Make a datasheet for each module Show FPGA design in terms of modules Describe internal circuitry Describe state machines Describe FPGA connections Describe synthesis results Provide timing spec for external timing analysis Show requirements of external circuitry Suggestions for FPGA Design Presentation

1. Modularize your design Easier to do during design phase Goal is to describe design in terms of components that can be individually verified Each component, or module, is a separate VHDL entity Modules should be of moderate, e.g., MSI, size E.g., FIFO, ALU Counter, decoder probably too small VME interface too big Suggestions for FPGA Design Presentation

2. Make a datasheet for each module Describe the module’s behavior Show truth table Show timing diagrams of operation Provide test bench used to verify module Model: MSI part data sheet Suggestions for FPGA Design Presentation

3. Show FPGA design in terms of modules Provide requirements spec for FPGA Draw block diagram Top-level VHDL entity shows FPGA inputs and outputs and ties component modules together Show necessary timing diagrams Interaction between modules Interaction with external circuitry Text for theory of operation Provide test bench for FPGA-level VHDL simulation Suggestions for FPGA Design Presentation

4. Describe internal circuitry Use of clock resources Discuss skew issues Describe deviations from fully synchronous design Be prepared to show necessary analysis Show how asynchronism is handled External signals Between clock domains Glitch analysis of output signals used as clocks by other parts Suggestions for FPGA Design Presentation

5. Describe state machines Encoding chosen Protection against lock-up states Homing sequences Reset conditions Suggestions for FPGA Design Presentation

6. Describe FPGA connections Use of special pins: TRST*, MODE, etc. Power supply requirements Levels, sequencing, etc. Termination of unused clock pins Input and output options chosen for pins Discuss transition times of inputs POR operation and circuitry Critical signals and power-up conditions Remember WIRE! Suggestions for FPGA Design Presentation

7. Describe synthesis results Percentage of utilization Flip-flop replication and its effects on reliable operation Margin results from Timer Timing of circuits using both clock edges Suggestions for FPGA Design Presentation

8. Provide timing spec for external timing analysis Tsu, Th with respect to clock Clock to output Tpd Tpw for signals connected to flip-flop clocks Clock symmetry requirements if both edges of clock used Suggestions for FPGA Design Presentation

9. Show requirements of external circuitry Provide data sheets for parts interfacing to FPGA Show timing diagrams of interactions of FPGA to other parts Suggestions for FPGA Design Presentation

Suggestions for FPGA Design Presentation References Design guidelines: http://klabs.org/DEI/References/design_guidelines/nasa_guidelines/index.htm Design tutorials http://klabs.org/richcontent/Tutorial/tutorial.htm Design, analysis, and test guidelines: http://klabs.org/DEI/References/design_guidelines/design_analysis_test_guides.htm Suggestions for FPGA Design Presentation