Advanced Implantation Detector Array (AIDA): Project Summary & Status Tom Davinson School of Physics & Astronomy The University of Edinburgh presented by Tom Davinson on behalf of the AIDA collaboration (Edinburgh – Liverpool – STFC DL & RAL)

AIDA Project Project web site The University of Edinburgh (lead RO) Phil Woods et al. The University of Liverpool Rob Page et al. STFC DL & RAL John Simpson et al. Project Manager: Tom Davinson Project commenced: September 2006

DESPEC: Implantation DSSD Concept SuperFRS, Low Energy Branch (LEB) Exotic nuclei – energies ~ 50 – 200MeV/u Implanted into multi-plane, highly segmented DSSD array Implant – decay correlations Multi-GeV DSSD implantation events Observe subsequent p, 2p, , , ,  p,  n … decays Measure half lives, branching ratios, decay energies … Tag interesting events for gamma and neutron detector arrays

Implantation DSSD Configurations Two configurations proposed: a)8cm x 24cm “cocktail” mode many isotopes measured simultaneously b) 8cm x 8cm high efficiency mode concentrate on particular isotope(s)

AIDA: DSSD Array Design 8cm x 8cm DSSDs common wafer design for 8cm x 24cm and 8cm x 8cm configurations 8cm x 24cm 3 adjacent wafers – horizontal strips series bonded 128 p+n junction strips, 128 n+n ohmic strips per wafer strip pitch 625  m wafer thickness 1mm  E, Veto and up to 6 intermediate planes 4096 channels (8cm x 24cm) overall package sizes (silicon, PCB, connectors, enclosure … ) ~ 10cm x 26cm x 4cm or ~ 10cm x 10cm x 4cm courtesy B.Rubio

ASIC Design Requirements Selectable gain MeV FSR Low noise keV FWHM energy measurement of implantation and decay events Selectable threshold< 0.25 – 10% FSR observe and measure low energy  detection efficiency Integral non-linearity 95% FSR spectrum analysis, calibration, threshold determination Autonomous overload detection & recovery ~  s observe and measure fast implantation – decay correlations Nominal signal processing time < 10  s observe and measure fast decay – decay correlations Receive (transmit) timestamp data correlate events with data from other detector systems Timing trigger for coincidences with other detector systems DAQ rate management, neutron ToF

Schematic of Prototype ASIC Functionality Note – prototype ASIC will also evaluate use of digital signal processing Potential advantages decay – decay correlations to ~ 200ns pulse shape analysis ballistic deficit correction

High (20MeV FSR), intermediate (1GeV FSR) and low gain (20GeV FSR) channels in parallel Blocks are sequenced to follow signal’s flow (“left to right”) Shaper and peak hold at back end to minimize noise 400  m x 6mm 400  m ~6mm Preamplifiers + feedback 700pF feedback capacitor High speed buffer Fast comparators Slow comparator Shapers Peak Holds + MUX Prototype AIDA ASIC: Channel Layout

Analogue inputs left edge Control/outputs right edge Power/bias top and bottom 16 channels per ASIC Prototypes delivered May 2009 MPW run 100 dies delivered Functional tests at STFC RAL OK Prototype AIDA ASIC: Top level design

Prototype AIDA ASIC: Analogue input and bias reference

Prototype AIDA ASIC: Analogue outputs

Prototype AIDA ASIC

Input signals (voltage step capacitive-coupled) Preamp buffered output (Low-Medium Energy Channel) Trigger output “Data Ready” signal Variable medium-energy (ME) event followed after 5us by a second fixed ME event: the energy of the first event (11.75pC, 23.5pC, 35.25pC) does not affect the response to the second (11.75pC). 1: Medium Energy (ME) + ME

Input signals (voltage step capacitive-coupled) Analog output (peak-hold multiplexed output) Trigger output “Data Ready” signal When the data ready signal is active, the correct value is present at the analogue output (after the hit has been detected and the correct address been fed into the output multiplexer). NB: the test environment is very noisy and that affects the measurements. 1: Medium Energy (ME) + ME

Three high-energy (HE) events (610pC, 430pC, 250pC) followed by a ME event (28.8pC): the initial HE event does not affect the response to the second. [The roll-of of the L-ME channel preamplifier is due to the HE channel amplifier becoming active: the two are effectively in parallel. Note the Range signal changing status after the HE event] Input signals (voltage step capacitive-coupled) Preamp buffered output (Low-Medium Energy Channel) “Range” signal High = high-energy channel active “Data Ready” signal 2: High Energy (HE) + ME

Analog output (peak-hold multiplexed output) “Data Ready” signal Although the low-medium energy channel preamp saturates, the correct value is stored and multiplexed to the Analog Output when the “Data Ready” signal is active. Preamp buffered output (Low-Medium Energy Channel) 2: High Energy (HE) + ME

Fixed high-energy (HE) event (610pC) followed by three ME events (15pC, 30pC, 45pC): the ASIC recovers autonomously from the overload of the L-ME channel and the second event is read correctly. Input signals (voltage step capacitive-coupled) Preamp buffered output (Low-Medium Energy Channel) “Range” signal High = high-energy channel active “Data Ready” signal 3: High Energy (HE) + ME

Fixed high-energy (HE) event (610pC) followed by three ME events (15pC, 30pC, 45pC): the ASIC recovers autonomously from the overload of the L-ME channel and the second event is read correctly. Input signals (voltage step capacitive-coupled) Preamp buffered output (Low-Medium Energy Channel) “Range” signal High = high-energy channel active “Data Ready” signal 3: High Energy (HE) + ME

First value (constant) given by the High-Energy channel, second by the Medium-Energy channel. Input signals (voltage step capacitive-coupled) “Range” signal High = high-energy channel active “Data Ready” signal Analog output (peak-hold multiplexed output) 3: High Energy (HE) + ME

4x AIDA ASICs 64 channels Design complete Delivery November 9 20 units Prototype AIDA Mezzanine

Prototype AIDA FEE Multiplex readout Digital readout FPGA, Memory, Gbit Clock distribution Power Supplies Mezzanine Design complete Production complete 8 units (4x AIDA, 2x DL DDG, 2x LYCCA) Delivered week commencing

Prototype FEE card Initial tests underway (STFC DL DDG) - FPGA Virtex 5 configuration - PowerPC with internal memory & terminal - DDR2 memory tests - Gbit ethernet - ASIC comms and discriminator timing - Analog buffers & ADCs - etc

FEE Assembly Sequence

Prototype AIDA Enclosure Prototype mechanical design Based on 8cm x 8cm DSSSD evaluate prior to design for 24cm x 8cm DSSSD Compatible with RISING, TAS, 4  neutron detector 12x 8cm x 8cm DSSSDs 24x AIDA FEE cards 3072 channels Design complete Mechanical assembly in progress

Prototype AIDA Enclosure - Design drawings (PDF) available

AIDA Project Timeline November/December 2009 Systems integration (ASIC+Mezzanine+FEE) Bench tests February 2010 In-beam tests March 2010 Design revisions April 2010 ASIC engineering run FEE production run June 2010 Production delivery complete

Acknowledgements My thanks to: STFC DLIan Lazarus, Patrick Coleman-Smith, Jonathan Strachan & Paul Morrall STFC RAL Steve Thomas & Davide Braga Edinburgh Zhong Liu Liverpool Dave Seddon, Sami Rinta-Antila & Rob Page

Prototype AIDA FEE:

Design Study Conclusions 4’’ or 6” Si wafer technology? - integrated polysilicon bias resistors (15M  ) - separate coupling capacitors (require 22nF/200V+) Radiation damage mitigation measures essential - detector cooling required Noise specification (12keV FWHM) … “not unreasonable” Discriminator - low threshold ( 100nA - separate timing discriminator – higher threshold x1000 overload recovery ~  s achievable - depends on input pulse shape - optimisation requires more information