XTRP Hardware Mike Kasten University of Illinois 2/24/00

Data board (x12) Clock/control board Clock/control transition module Data board transition module (x12) CDF clock Data boards (duplicates) 2 XFT linkers L1 muon L1 calorimetry Level1 Request 132 ns + 33ns clocks SVT L2 trigger 12 data boards 30 ° (2 wedges) The core XTRP System XTRP I/O Internal communication Track Data

XTRP Teststand #1: Pre-crate Custom Backplane Initial power-up Boot PROM VME emulation –Signals via Unidig Module –C code Power measurement U of Illinois

XTRP Teststand #1: VME crate Successfully completed VME transactions –Write/Read registers –Load extrapolation RAMs Benchtop accessibility & VME emulation were extremely helpful for initial debugging This teststand will provide initial testing infrastructure for new VME boards

XTRP Teststand #2: VME crate VIPA-style Test Crate at U of Illinois VME access –Write/Read registers –Load extrapolation RAMs Multi-board system –Controller / TestClock / Clock Control / Data –Send clock signals from Clock Board to Data Board –Step data through Data Board (slow clock) Software Development –DataBSim.java (Data Board simulator) –XtrpExpertPanel.java (Test engine)

XTRP Functional Clock Test VME write (+Test Clock) TestClock Clock Board 132ns Clock Data Board 132ns, 33ns, Sync Signals CLOCK TEST 132ns, 33ns, Sync Signals

Set up Data Board & Clock Board Repeat N times: –Load XFT Simulation data into Data Board –Increment Data Board clock via Clock Board –Increment Simulator Compare Data Board versus Simulator Debug Functional Data Test Procedure

XTRP Functional Data Test VME write Test Clock Clock Board Data Board VME read & compare to Simulation STEPPED 132ns, 33ns, Sync Signals VME write XFT Simulation Data

XTRP Teststand #2: VME crate Data Board II is necessary –simple reroutes: ~100 power supply pins (64 identical ICs ) various –Mechanical compliance –Improvements (JTAG & buffering) Data Board I lives on… –Completely Functional –Acceptable to use for B0 integration tests Clock Control Board is OK (so far) –Corrections do exist: ~25 total wires –Relayout not planned

XTRP Teststand #3: Wilson Hall Multi-crate system –XFT CDF-style Crate Test Clock / Clock Splitter / Controller / TRACER LinkerTester Linker / Output Modules –XTRP VIPA-style Crate Controller / TRACER Data Board Clock Control Board Much much more Software Development

XTRP Tests VME write Linker(2) Output Formatters Data Board VME read from Pipe FPGAs Data transferred at full speed for 250 clocks Linkertester Input Fifos INPUT TEST VME read & compare to Simulation CAL/MUON Data DATA TEST >100,000,000 clocks errors: x to xFFFFFF >1,000,000 clocks error free

XTRP Tests Linkertesters (2) Output Fifos Input Fifos VME write VME read & compare to Simulation Linkers (2) Data Board Data transferred at full speed for 10k clocks >10,000,000 clocks error free

XTRP Tests Linkertester Output Fifos Input Fifos VME write VME read & compare to Simulation Data Board Data transferred at full speed for 10k clocks Software under development

XTRP Teststand #3: Wilson Hall Data Board I –No more layout errors found Data Board Transition Module - new board necessary –wiring corrections: ~5 –PCB footprint for Muon connector is wrong Clock Board –No more layout errors found Clock Board Transition Module - new board necessary –Errors found independent of testing

Plan for New Hardware Data Board II –Quotes requested, waiting for responses –Contract Assembler reviewing BOM –Target date for 1st DBII: April 1, 2000 Data Board Transition Module –Want to connect to Muon & Calorimetry systems first –Target date for new TM: April 15, 2000 Clock Board Transition Module –Need a new board for SVT & L2P integration –Target date for new TM: May 1, 2000

Input Test Error Linker(2) Output Formatters x to xFFFFFF Data Board Transition Module 3.3V LVDS Receiver 3.3V LVTH Latch Backplane xFFFFEF xFFFFFF Error seen on only 1 out of 96 bits