Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. C H A P T E R 14 Advanced MOS and Bipolar Logic Circuits.

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Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. C H A P T E R 14 Advanced MOS and Bipolar Logic Circuits

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure 14.1 (a) The pseudo-NMOS logic inverter. (b) The enhancement-load (or saturated-load) NMOS inverter. (c) The depletion-load NMOS inverter.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure 14.2 Graphical construction to determine the VTC of the inverter in Fig. 14.1(a).

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure 14.3 VTC for the pseudo-NMOS inverter. This curve is plotted for V DD = 5 V, V tn = −V tp = 1 V, and r = 9.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure 14.4 NOR and NAND gates of the pseudo-NMOS type.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure 14.5 Conceptual pass-transistor logic gates. (a) Two switches, controlled by the input variables B and C, when connected in series in the path between the input node to which an input variable A is applied and the output node (with an implied load to ground) realize the function Y = ABC. (b) When the two switches are connected in parallel, the function realized is Y = A(B + C).

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure 14.6 Two possible implementations of a voltage-controlled switch connecting nodes A and Y: (a) single NMOS transistor and (b) CMOS transmission gate.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure 14.7 A basic design requirement of PTL circuits is that every node have, at all times, a low resistance path to either ground or V DD. Such a path does not exist in (a) when B is low and S 1 is open. It is provided in (b) through switch S 2.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure The use of transistor Q R, connected in a feedback loop around the CMOS inverter, to restore the V OH level, produced by Q 1, to V DD.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure The CMOS transmission gate and its circuit symbol.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure (a) A transmission gate connects the output of a CMOS inverter to the input of another. (b) Equivalent circuit for the purpose of analyzing the propagation delay of the circuit in (a).

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure A three-section RC ladder network.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure Realization of a two-to-one multiplexer using pass-transistor logic.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure Realization of the XOR function using pass-transistor logic.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure An example of a pass-transistor logic gate utilizing both the input variables and their complements. This type of circuit is therefore known as complementary pass-transistor logic, or CPL. Note that both the output function and its complement are generated.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure (a) Basic structure of dynamic-MOS logic circuits. (b) Waveform of the clock needed to operate the dynamic logic circuit. (c) An example circuit.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure Circuits for Example 14.3.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure (a) Charge sharing. (b) Adding a permanently turned-on transistor Q L solves the charge sharing problem at the expense of static power dissipation.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure Two single-input dynamic logic gates connected in cascade. With the input A high, during the evaluation phase C L2 will partially discharge and the output at Y 2 will fall lower than V DD, which can cause logic malfunction.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure E 14.10

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure The Domino CMOS logic gate. The circuit consists of a dynamic-MOS logic gate with a static-CMOS inverter connected to the output. During evaluation, Y either will remain low (at 0 V) or will make one 0-to-1 transition (to V DD ).

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure (a) Two single-input Domino CMOS logic gates connected in cascade. (b) Waveforms during the evaluation phase.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure The basic element of ECL is the differential pair. Here, V R is a reference voltage.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure E14.12

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure Basic circuit of the ECL 10K logic-gate family.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure The proper way to connect high-speed logic gates such as ECL. Properly terminating the transmission line connecting the two gates eliminates the “ringing” that would otherwise corrupt the logic signals. (See Section )

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure Simplified version of the ECL gate for the purpose of finding transfer characteristics.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure Circuit for determining V OH.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure Equivalent circuit for determining the temperature coefficient of the reference voltage V R.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure Equivalent circuit for determining the temperature coefficient of V OL

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure Equivalent circuit for determining the temperature coefficient of V OH.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure The wired-OR capability of ECL.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure Development of the BiCMOS inverter circuit. (a) The basic concept is to use an additional bipolar transistor to increase the output current drive of each of Q N and Q P of the CMOS inverter. (b) The circuit in (a) can be thought of as utilizing these composite devices. (c) To reduce the turn-off times of Q 1 and Q 2, “bleeder resistors” R 1 and R 2 are added. (d) Implementation of the circuit in (c) using NMOS transistors to realize the resistors. (e) An improved version of the circuit in (c) obtained by connecting the lower end of R 1 to the output node.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure Equivalent circuits for charging and discharging a load capacitance C. Note that C includes all the capacitances present at the output node.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure A BiCMOS two-input NAND gate.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure P 14.1

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure P14.14

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure P14.18

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure P14.23

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure P14.34

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure P14.44