Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Topics n Standard cell-based layout. n Channel routing. n Simulation.

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Standard cell layout n Layout made of small cells: gates, flip- flops, etc. n Cells are hand-designed. n Assembly of cells is automatic: –cells arranged in rows; –wires routed between (and through) cells.

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Standard cell structure VDD VSS n tub p tub Intra-cell wiring pullups pulldowns pin Feedthrough area

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Standard cell design n Pitch: height of cell. –All cells have same pitch, may have different widths. n VDD, VSS connections are designed to run through cells. n A feedthrough area may allow wires to be routed over the cell.

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Single-row layout design Routing channel cell wireHorizontal track Vertical track height

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Routing channels n Tracks form a grid for routing. –Spacing between tracks is center-to-center distance between wires. –Track spacing depends on wire layer used. n Different layers are (generally) used for horizontal and vertical wires. –Horizontal and vertical can be routed relatively independently.

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Routing channel design n Placement of cells determines placement of pins. n Pin placement determines difficulty of routing problem. n Density: lower bound on number of horizontal tracks needed to route the channel. –Maximum number of nets crossing from one end of channel to the other.

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Pin placement and routing before abc bca abc bca Density = 3 Density = 2

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Example: full adder layout n Two outputs: sum, carry. sum carry x1 x2 n1 n2 n3 n4

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Layout methodology n Generate candidates, evaluate area and speed. –Can improve candidate without starting from scratch. n To generate a candidate: –place gates in a row; –draw wires between gates and primary inputs/outputs; –measure channel density.

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf A candidate layout x1x2n1n2n3n4 a b c s cout Density = 5

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Improvement strategies n Swap pairs of gates. –Doesn’t help here. n Exchange larger groups of cells. –Swapping order of sum and carry groups doesn’t help either. n This seems to be the placement that gives the lowest channel density. –Cell sizes are fixed, so channel height determines area.

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Left-edge algorithm n Basic channel routing algorithm. n Assumes one horizontal segment per net. n Sweep pins from left to right: –assign horizontal segment to lowest available track.

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Example ABC ABBC

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Limitations of left-edge algorithm n Some combinations of nets require more than one horizontal segment per net. BA AB aligned ?

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Vertical constraints n Aligned pins form vertical constraints. –Wire to lower pin must be on lower track; wire to upper pin must be above lower pin’s wire. BA AB

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Dogleg wire n A dogleg wire has more than one horizontal segment. BA AB

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Rat’s nest plot n Can be used to judge placement before final routing.

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Simulation n Goals of simulation: –functional verification; –timing; –power consumption; –testability.

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Types of simulation n Circuit simulation: –analog voltages and currents. n Timing simulation: –simple analog models to provide timing but not detailed waveforms. n Switch simulation: –transistors as semi-ideal switches.

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Types of simulation, cont’d. n Gate simulation: –logic gates as primitive elements. n Models for gate simulation: –zero delay; –unit delay; –variable delay. n Fault simulation: –models fault propagation (more later).

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Example: switch simulation a + + b c d c X X X o 0 1 1

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Example, cont’d. a + + b c d c o