ECE 545 Project 1 Part IV Key Scheduling Final Integration List of Deliverables.

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ECE 545 Project 1 Part IV Key Scheduling Final Integration List of Deliverables

RC5 – Key Scheduling

RC5 - Key Scheduling Initialize and Convert Initialize t = 2  r + 2 c = 8b8b w S[0] = P w for i=1 to t-1 do S[i] = S[i-1] + Q w Convert for i=0 to c-1 do L[i] = 0; Copy key bits directly to the memory positions represented by L.

Mix i = j = 0 A = B = 0 do 3  max{t, c} times { A = S[i] = (S[i] + A + B) <<< 3 B = L[j] = (L[j] + A + B) <<< (A+B) i = (i+1) mod t j = (j+1) mod c } RC5 - Key Scheduling Mix

Part IV due Thursday November 18, 3 PM 1.Describe a control unit of the RC5 key scheduling circuit and its interface to the memory of round keys using a block diagram and/or ASM chart. 2.Translate the block diagram and the ASM chart into synthesizable RTL VHDL code. 3.Write a testbench capable of verifying the function of the designed control unit. 4. Verify the correctness of your VHDL codes using functional simulation, synthesis, and timing simulation for the case of RC5 32/12/16.

Encryption/decryption unit with control & i/o interface clock reset encrypt/decrypt data input data available data read m key input key available key read k Key scheduling unit Key memory data output write full m round key(s) round number round key(s) cycle number

Final Integration & Report due Monday, November 22, 4 PM 1.Integrate together all synthesizable portions of your VHDL code describing RC5. 2.Write a testbench capable of verifying the operation of your entire RC5 implementation. This testbench should be able to read RC5 test vectors (inputs and outputs) from a file, and generate as a result the messages: “circuit operating correctly” or “circuit operating incorrectly: input x, expected output y1, actual output y2”. 3.Perform the functional simulation of your circuit and store timing waveforms for a. RC5 32/12/16 b. RC5 64/20/32

5.Synthesize and implement your entire circuit for a. RC5 32/12/16 b. RC5 64/20/32 Use the smallest device of the Xilinx Spartan 2 family capable of holding the bigger of the two circuits. 6. For both implemented circuits, determine - maximum clock frequency - maximum encryption/decryption throughput - area in the number of CLB slices - ratio: maximum encryption/decryption throughput divided by area. 7. Verify the correct operation of both versions of the RC5 circuit using timing simulation at the frequency closed to the maximum clock frequency. Store the obtained timing waveforms.

Final Deliverables 1.All synthesizable VHDL source codes. 2.All testbenches used to verify the operation of the entire circuit and its components, including corresponding input files containing test vectors. 3.All block diagrams, state diagrams, and ASM charts describing the entire circuit and its components. 4.Timing waveforms demonstrating the correct operation of the entire circuit and its components. 5.Final report containing the description of the source of test vectors any diversions from the project specification obtained results discussion of the encountered problems, and issues remaining to be resolved.