Voltage Divider Bias ENGI 242 ELEC 222

23 February 2005ENGI 242/ELEC 2222 BJT Biasing 3 For the Voltage Divider Bias Configurations Draw Equivalent Input circuit Draw Equivalent Output circuit Write necessary KVL and KCL Equations Determine the Quiescent Operating Point –Graphical Solution using Load lines –Computational Analysis Design and test design using a computer simulation

23 February 2005ENGI 242/ELEC 2223 Voltage-divider bias configuration

23 February 2005ENGI 242/ELEC 2224 Voltage Divider Input Circuit Approximate Analysis This method is valid only if R 2 .1  R E Under these conditions R E does not significantly load R 2 and it may be ignored: I B << I 1 and I 2 and I 1  I 2 Therefore: We may apply KVL to the input, which gives us: -V B + V BE + I E R E = 0 Solving for I E we get:

23 February 2005ENGI 242/ELEC 2225 Input Circuit Exact Analysis This method is always valid must be used when R 2 >.1  R E Perform Thevenin’s Theorem Open the base lead of the transistor, and the Voltage Divider bias circuit is: Calculate R TH We may apply KVL to the input, which gives us: -V TH + I B R TH + V BE + I E R E = 0 Since I E = (  + 1) I B

23 February 2005ENGI 242/ELEC 2226 Redrawing the input circuit for the network

23 February 2005ENGI 242/ELEC 2227 Determining V TH

23 February 2005ENGI 242/ELEC 2228 Determining R TH

23 February 2005ENGI 242/ELEC 2229 The Thévenin Equivalent Circuit Note that V E = V B – V BE and I E = (  + 1)I B

23 February 2005ENGI 242/ELEC Input Circuit Exact Analysis We may apply KVL to the input, which gives us: -V TH + I B R TH + V BE + I E R E = 0 Since I E = (  + 1) I B

23 February 2005ENGI 242/ELEC Collector-Emitter Loop

23 February 2005ENGI 242/ELEC Collector-Emitter (Output) Loop Applying Kirchoff’s voltage law: - V CC + I C R C + V CE + I E R E = 0 Assuming that I E  I C and solving for V CE : Solve for V E : V E = I E R E Solve for V C : V C = V CC - I C R C or V C = V CE + I E R E Solve for V B : V B = V CC - I B R B or V B = V BE + I E R E

23 February 2005ENGI 242/ELEC Voltage Divider Bias Example 1 V CC = 22V R 1 = 39k  R 2 = 3.9k  R C = 10k  R E = 1.5k   = 140

23 February 2005ENGI 242/ELEC Voltage Divider Bias Example 2 V CC = 18V R 1 = 39k  R 2 = 8.2k  R C = 3.3k  R E = 1k   = 120

23 February 2005ENGI 242/ELEC Voltage Divider Bias Example 3 V CC = 16V R 1 = 62k  R 2 = 9.1k  R C = 3.9k  R E =.68k   = 80

23 February 2005ENGI 242/ELEC Design of CE Amplifier with Voltage Divider Bias 1.Select a value for V CC 2.Determine the value of  from spec sheet or family of curves 3.Select a value for I CQ 4.Let V CE = ½ V CC (typical operation, 0.4 V CC ≤ V C ≤ 0.6 V CC ) 5.Let V E = 0.1 V CC (for good operation, 0.1 V CC ≤ V E ≤ 0.2 V CC ) 6.Calculate R E and R C 7.Let R 2 ≤ 0.1  R E (for this calculation, use low value for  ) 8.Calculate R 1

23 February 2005ENGI 242/ELEC CE Amplifier Design Design a Common Emitter Amplifier with Voltage Divider Bias for the following parameters: V CC = 24V I C = 5mA V E =.1V CC V C =.55V CC  = 135

23 February 2005ENGI 242/ELEC 22218

23 February 2005ENGI 242/ELEC CE Amplifier Design

23 February 2005ENGI 242/ELEC CE Amplifier Design Voltage Divider Bias

Collector Feedback Bias ENGI 242 ELEC 222

23 February 2005ENGI 242/ELEC BJT Biasing 4 For the Collector Feedback Bias Configuration: Draw Equivalent Input circuit Draw Equivalent Output circuit Write necessary KVL and KCL Equations Determine the Quiescent Operating Point –Graphical Solution using Loadlines –Computational Analysis Design and test design using a computer simulation

23 February 2005ENGI 242/ELEC DC Bias with Collector (Voltage) Feedback Another way to improve the stability of a bias circuit is to add a feedback path from collector to base In this bias circuit the Q-point is only slightly dependent on the transistor 

23 February 2005ENGI 242/ELEC Base – Emitter Loop Solve for I B Applying Kirchoff’s voltage law: -V CC + I C R C + I B R B + V BE + I E R E = 0 Note: I C = I E = I C + I B Since I E = (  + 1) I B then: -V CC + (  + 1)I B R C + I B R B + V BE (  + 1)I B R E = 0 Simplifying and solving for I B :

23 February 2005ENGI 242/ELEC Applying Kirchoff’s voltage law: -V CC + I E R C + I B R B + V BE + I E R E = 0 Since I E = (  + 1) I B then: Simplifying and solving for I E : Base – Emitter Loop Solve for I E

23 February 2005ENGI 242/ELEC Collector Emitter Loop Applying Kirchoff’s voltage law: I E R E + V CE + I C R C – V CC = 0 Since I C = I E and I E = (  + 1) I B : I E (R C + R E ) + V CE – V CC =0 Solving for V CE :V CE = V CC – I E (R E + R C )

23 February 2005ENGI 242/ELEC Network Example

23 February 2005ENGI 242/ELEC Network Example

23 February 2005ENGI 242/ELEC Collector feedback with R E = 0 

23 February 2005ENGI 242/ELEC Design of CE Amplifier with Collector Feedback Bias 1.Select a value for V CC 2.Determine the value of  from spec sheet or family of curves 3.Select a value for I EQ 4.Let V CE = ½ V CC (typical operation, 0.4 V CC ≤ V C ≤ 0.6 V CC ) 5.Let V E = 0.1 V CC (for good operation, 0.1 V CC ≤ V E ≤ 0.2 V CC ) 6.Calculate R E, R C and R B

Common Emitter Bias with Dual Supplies

23 February 2005ENGI 242/ELEC Voltage Divider Bias with Dual Power Supply

23 February 2005ENGI 242/ELEC Voltage Divider Bias with Dual Power Supply Input Circuit Find V TH and R TH

23 February 2005ENGI 242/ELEC Voltage Divider Bias with Dual Power Supply Output Circuit

23 February 2005ENGI 242/ELEC Voltage Divider Bias with Dual Power Supply

PSpice Simulation

23 February 2005ENGI 242/ELEC PSpice Bias Point Simulation

23 February 2005ENGI 242/ELEC PSpice Simulation for DC Bias

23 February 2005ENGI 242/ELEC PSpice Simulation for DC Sweep

23 February 2005ENGI 242/ELEC PSpice Simulation for DC Sweep The response of V CE demonstrates that it reaches a peak value near the Q point and then decreases The response of V C demonstrates rises rapidly towards the Q Point and then increases gradually towards a maximum value

23 February 2005ENGI 242/ELEC PSpice Simulation for AC Sweep

23 February 2005ENGI 242/ELEC PSpice Simulation for AC Sweep