Budapest University of Technology and Economics eet.bme.hu Department of Electron Devices A. Timár, M. Rencz Temperature dependent timing in standard cell.

Slides:

Advertisements

Similar presentations

Multi-stage Amplifiers

Advertisements

Tunable Sensors for Process-Aware Voltage Scaling

OCV-Aware Top-Level Clock Tree Optimization

VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects Sarangi et al Prateeksha Satyamoorthy CS

Supply Voltage Noise Aware ATPG for Transition Delay Faults Nisar Ahmed and M. Tehranipoor University of Connecticut Vinay Jayaram Texas Instruments, TX.

Improving Placement under the Constant Delay Model Kolja Sulimma 1, Ingmar Neumann 1, Lukas Van Ginneken 2, Wolfgang Kunz 1 1 EE and IT Department University.

Anjali Supekar *, Mohita Batra *, Rakesh Gulati *, Shahabuddin Qureshi °, Hina Mushir #, Prashant Pandey #, Samant Paul °, Seema Jaiswal ° * Automation.

Ch.3 Overview of Standard Cell Design

PERFECT Empower Project: Prototype Software Releases PI: Massoud Pedram Co-PIs: Murali Annavaram and Kaushik Roy (Purdue) July 17, 2014.

ECAD Tool Flows These notes are taken from the book: It’s The Methodology, Stupid! by Pran Kurup, Taher Abbasi, Ricky Bedi, Publisher ByteK Designs,

Minimal Skew Clock Embedding Considering Time-Variant Temperature Gradient Hao Yu, Yu Hu, Chun-Chen Liu and Lei He EE Department, UCLA Presented by Yu.

1 Closed-Loop Modeling of Power and Temperature Profiles of FPGAs Kanupriya Gulati Sunil P. Khatri Peng Li Department of ECE, Texas A&M University, College.

Digital Integrated Circuits© Prentice Hall 1995 Timing ISSUES IN TIMING.

Timing Analysis Timing Analysis Instructor: Dr. Vishwani D. Agrawal ELEC 7770 Advanced VLSI Design Team Project.

Power-Aware Placement

1 Variability Characterization in FPGAs Brendan Hargreaves 10/05/2006.

A Timing-Driven Soft-Macro Resynthesis Method in Interaction with Chip Floorplanning Hsiao-Pin Su 1 2 Allen C.-H. Wu 1 Youn-Long Lin 1 1 Department of.

Constructing Current-Based Gate Models Based on Existing Timing Library Andrew Kahng, Bao Liu, Xu Xu UC San Diego

Chung-Kuan Cheng†, Andrew B. Kahng†‡,

On-Line Adjustable Buffering for Runtime Power Reduction Andrew B. Kahng Ψ Sherief Reda † Puneet Sharma Ψ Ψ University of California, San Diego † Brown.

S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 22: Material Review Prof. Sherief Reda Division of Engineering, Brown University.

Logic Design Outline –Logic Design –Schematic Capture –Logic Simulation –Logic Synthesis –Technology Mapping –Logic Verification Goal –Understand logic.

An Introduction to Synopsys Design Automation Jeremy Lee November 7, 2007.

King Fahd University of Petroleum and Minerals Computer Engineering Department COE 561 Digital Systems Design and Synthesis (Course Activity) Synthesis.

1 DESIGN OF 8-BIT ALU Vijigish Lella Harish Gogineni Bangar Raju Singaraju Advisor: Dr. David W. Parent 8 May 2006.

Laboratory of Reliable Computing Department of Electrical Engineering National Tsing Hua University Hsinchu, Taiwan Delay Defect Characteristics and Testing.

Temperature-Aware Design Presented by Mehul Shah 4/29/04.

 Distortion – the alteration of the original shape of a waveform.  Function of distortion analyzer: measuring the extent of distortion (the o/p differs.

Enhanced Metamodeling Techniques for High-Dimensional IC Design Estimation Problems Andrew B. Kahng, Bill Lin and Siddhartha Nath VLSI CAD LABORATORY,

ECE 331 – Digital System Design Power Dissipation and Propagation Delay.

Design Tools, Flows and Library Aspects during the FE-I4 Implementation on Silicon Vladimir Zivkovic National Institute for Subatomic Physics Amsterdam,

8/16/2015\course\cpeg323-08F\Topics1b.ppt1 A Review of Processor Design Flow.

Supply Voltage Biasing in Synopsys Andy Whetzel University of Virginia 1.

INTEGRATED CIRCUIT LOGIC FAMILY

Capturing Crosstalk-Induced Waveform for Accurate Static Timing Analysis Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera Kyoto University.

COE4OI5 Engineering Design. Copyright S. Shirani 2 Course Outline Design process, design of digital hardware Programmable logic technology Altera’s UP2.

Total Dose Effects on Devices and Circuits - Principles and Limits of Ground Evaluation-

Budapesti University of Technology and Economics Department of Electron Devices eet.bme.hu THERMINATOR – Training Gergely Nagy Catania,

ASIC Design Flow – An Overview Ing. Pullini Antonio

1 5. Application Examples 5.1. Programmable compensation for analog circuits (Optimal tuning) 5.2. Programmable delays in high-speed digital circuits (Clock.

HDL-Based Layout Synthesis Methodologies Allen C.-H. Wu Department of Computer Science Tsing Hua University Hsinchu, Taiwan, R.O.C {

1 5. Application Examples 5.1. Programmable compensation for analog circuits (Optimal tuning) 5.2. Programmable delays in high-speed digital circuits (Clock.

S.Veneziano – INFN Roma July 2003 TDAQ week CMA LVL1 Barrel status ATLAS TDAQ week July 2003.

Interconnect Focus Center e¯e¯ e¯e¯ e¯e¯ e¯e¯ IWSM 2001Sam, Chandrakasan, and Boning – MIT Variation Issues in On-Chip Optical Clock Distribution S. L.

VHDL Project Specification Naser Mohammadzadeh. Schedule  due date: Tir 18 th 2.

Chonnam national university VLSI Lab 8.4 Block Integration for Hard Macros The process of integrating the subblocks into the macro.

FPGAs for Temperature-Aware Microarchitecture Research Siva Velusamy, Wei Huang, John Lach, Mircea Stan and Kevin Skadron University of Virginia.

MICAS Department of Electrical Engineering (ESAT) Design-In for EMC on digital circuit December 5th, 2005 Low Emission Digital Circuit Design Junfeng Zhou.

The Chicago Half of Champ

CS/EE 3700 : Fundamentals of Digital System Design Chris J. Myers Lecture 4: Logic Optimization Chapter 4.

Supply Voltage Biasing Andy Whetzel and Elena Weinberg University of Virginia.

DEVICES AND DESIGN : ASIC. DEFINITION Any IC other than a general purpose IC which contains the functionality of thousands of gates is usually called.

Curtis A. Nelson 1 Technology Mapping of Timed Circuits Curtis A. Nelson University of Utah September 23, 2002.

A.M.E.N. Autonomous Meteorological Embedded Network for Fire Fighting Fan Zhang, Dmitry Stomakhin, Flavio Sira, Brian Hansen.

Budapest University of Technology and Economics Department of Electron Devices Microelectronics, BSc course MOS inverters

Principles of the Global Positioning System Lecture 08 Prof. Thomas Herring Room ;

ASIC/FPGA design flow. Design Flow Detailed Design Detailed Design Ideas Design Ideas Device Programming Device Programming Timing Simulation Timing Simulation.

1 Hardware Reliability Margining for the Dark Silicon Era Liangzhen Lai and Puneet Gupta Department of Electrical Engineering University of California,

CI Lecture Series Summer 2010 An Overview of IQ Modulation and Demodulation Techniques for Cavity LLRF Control.

Budapest University of Technology and Economics Department of Electron Devices eet.bme.hu Research and Development at the Ferenc Ender

Modelling LED Lamps with Thermal Phenomena Taken into Account Krzysztof Górecki and Przemysław Ptak Gdynia Maritime University Department of Marine Electronics.

Operational amplifier

Thermal Aware EM Computation

Introduction SISSI: Simulator for Integrated Structures by Simultaneous Iteration Experimental software package on top of a particular design kit within.

Library Characterization

VLSI Testing Lecture 5: Logic Simulation

Vishwani D. Agrawal Department of ECE, Auburn University

EMC problems of DSOI device and circuits

Timing Analysis 11/21/2018.

Circuit Design Techniques for Low Power DSPs

Presentation transcript:

Budapest University of Technology and Economics eet.bme.hu Department of Electron Devices A. Timár, M. Rencz Temperature dependent timing in standard cell designs 18th International Workshop on Thermal investigations of ICs and Systems (Therminic 2012) September 2012

eet.bme.hu © BME Department of Electron Devices, th International Workshop on Thermal investigations of ICs and Systems (2012) Problem description ►Calculating temperature dependent timing in standard cell designs is necessary ►Failing to take temperature dependent delays into account can fail timing closure and integrity ►Device temperature and self-heating during operation can offset cell delays resulting in timing failures ►E.g. clock skew, propagation delay changes ►Correct functional operation may fail 2 A. Timár, M. Rencz: Temperature dependent timing in standard cell designs September 2012

eet.bme.hu © BME Department of Electron Devices, th International Workshop on Thermal investigations of ICs and Systems (2012) Delay versus temperature data needed ►How to make connection between timing and temperature data? ►PVT variation data is available (Process, Voltage, Temperature) ►Standard cell libraries are characterized for a few PVT corners ►E.g. Supply voltage VDD = 4.5V…5V…5.5V Process mask variation = 0.9…1.0…1.1 Temperature = -40°C…27°C…125°C ►Intermediate points are calculated by linear interpolation 3 A. Timár, M. Rencz: Temperature dependent timing in standard cell designs September 2012

eet.bme.hu © BME Department of Electron Devices, th International Workshop on Thermal investigations of ICs and Systems (2012) Timing and delay data ►Standard cell libraries usually provide timing, noise and power data for PVT corners ►Liberty format (by Synopsys) ►Timing Library Format (TLF, by Cadence) ►Both contain the same data in different format ►Timing data for each cell and each corner can be extracted ►Delays should be modified according to temperature changes during logic simulation 4 A. Timár, M. Rencz: Temperature dependent timing in standard cell designs September 2012

eet.bme.hu © BME Department of Electron Devices, th International Workshop on Thermal investigations of ICs and Systems (2012) CellTherm logi-thermal simulator ►Latest enhancements of the CellTherm* logi-thermal simulator include: ►Temperature dependent delay calculation ►Delay back-annotation during simulation ►Partitioning and data serialization for simulation speedup 5 A. Timár, M. Rencz: Temperature dependent timing in standard cell designs September 2012 * CellTherm is researched and developed in the Department of Electron Devices, BME

eet.bme.hu © BME Department of Electron Devices, th International Workshop on Thermal investigations of ICs and Systems (2012) Delay annotation from SDF ►CellTherm connects a logic simulator and a thermal simulator and conveys data between them ►The delay data for actual corners are extracted from SDF (Standard Delay Format) files ►SDF files can be generated from the synthesis software ►Pre- and post-layout SDFs can be extracted ►Synthesis softwares calculate SDF data from the actual placement and (optional) routing of the standard cell design ►SDF data is derived from the Liberty database according to the PVT corners ►Result: SDF contains valid delay data for the specific design and corners 6 A. Timár, M. Rencz: Temperature dependent timing in standard cell designs September 2012

eet.bme.hu © BME Department of Electron Devices, th International Workshop on Thermal investigations of ICs and Systems (2012) Demonstration ►To demonstrate the necessity of temperature- aware timing simulation ►Simple demonstration circuit: ring oscillator ►Fictional standard cell library  Enlarged cell sizes  Increased power dissipations  Reduced temperature corner span ►To emphasize temperature dependent timing Ring oscillator 7 A. Timár, M. Rencz: Temperature dependent timing in standard cell designs September 2012

eet.bme.hu © BME Department of Electron Devices, th International Workshop on Thermal investigations of ICs and Systems (2012) Ring oscillator demonstration 8 A. Timár, M. Rencz: Temperature dependent timing in standard cell designs September 2012 NAND INVINV INVINV INVINV INVINV INVINV INVINV INVINV INVINV INVINV INVINV START OSC_OUT

eet.bme.hu © BME Department of Electron Devices, th International Workshop on Thermal investigations of ICs and Systems (2012) Delay vs Temperature functions ►Demonstrational SDF ►Temperature corners span reduced to visibly demonstrate temperature dependent delays 9 A. Timár, M. Rencz: Temperature dependent timing in standard cell designs September 2012

eet.bme.hu © BME Department of Electron Devices, th International Workshop on Thermal investigations of ICs and Systems (2012) Thermal and power maps ►Bi-linear interpolation of partition temperatures and dissipations result in smoother maps (like a 100x100 mesh) 10 A. Timár, M. Rencz: Temperature dependent timing in standard cell designs September 2012

eet.bme.hu © BME Department of Electron Devices, th International Workshop on Thermal investigations of ICs and Systems (2012) Cell temperatures over time 11 A. Timár, M. Rencz: Temperature dependent timing in standard cell designs September 2012

eet.bme.hu © BME Department of Electron Devices, th International Workshop on Thermal investigations of ICs and Systems (2012) Frequency of ring oscillator 12 A. Timár, M. Rencz: Temperature dependent timing in standard cell designs September 2012

eet.bme.hu © BME Department of Electron Devices, th International Workshop on Thermal investigations of ICs and Systems (2012) Summary ►The latest improvements and enhancements were introduced in the CellTherm logi-thermal simulator ►Temperature dependent delays can be calculated ►The delays can be back-annotated into the logic simulation during runtime ►A simple standard cell circuit has been made to demonstrate temperature-aware delay calculation ►The demonstration ring oscillator’s frequency changes with the self-heating of the circuit ►Delay-temperature curves are extracted from SDF files produced by synthesis software 13 A. Timár, M. Rencz: Temperature dependent timing in standard cell designs September 2012

eet.bme.hu © BME Department of Electron Devices, th International Workshop on Thermal investigations of ICs and Systems (2012) Possible further improvements ►Interpolating PVT corners results in rough delay calculations ►More accurate and precise timing and power characterization in function of temperature is needed to calculate self-heating induced timing variation ►Open source Liberty format can be extended to contain arbitrary number of temperature data points ►This would allow simulation of sub-nanometer process effects like inverse temperature dependency (ITD) during a logi-thermal simulation ►“Worst-case scenario is at maximum temperature” may not be true when ITD takes place 14 A. Timár, M. Rencz: Temperature dependent timing in standard cell designs September 2012

eet.bme.hu © BME Department of Electron Devices, th International Workshop on Thermal investigations of ICs and Systems (2012) Acknowledgement The work reported in this presentation was supported by ►The THERMINATOR Project of the FW7 program of the EU ►The Hungarian Government through the TÁMOP-4.2.1/B- 09/1/KMR project at the Budapest University of Technology and Economics 15 A. Timár, M. Rencz: Temperature dependent timing in standard cell designs September 2012