Tutorial I Circuit Simulation Boonchuay Supmonchai Integrated Design Application Research (IDAR) Laboratory June 24, 2005

B.Supmonchai Digital ICs SPICE Simulations 2 Outline  Introduction to SPICE  Basic Commands and elements in SPICE  SPICE MOSFET models  Device Characterization  Pitfalls and Fallacies

B.Supmonchai Digital ICs SPICE Simulations 3 Simulations in IC Processes  Fabricating chips is expensive and time-consuming; need good simulation CAD tools and hard work.ArchitectureCircuit Process Logic Level of Abstraction HighLow How factors in a process (e.g., time and temperature) affect device physical and electrical characteristics - SUPREME Use device models and netlist to predict circuit voltages and currents, which indicate performance and power consumption - SPICE Predict function of digital circuits and verify correct logical operation of designs - HDL Predict throughput and memory access patterns at the RTL, for design decision such as pipelining and cache organization

B.Supmonchai Digital ICs SPICE Simulations 4 Introduction to SPICE  SPICE  Simulation Program with Integrated Circuit Emphasis  Developed in 1970’s at Berkeley  Written in FORTRAN for punch-card machines  Circuits elements are called cards SPICE deck  Complete description is called a SPICE deck  SPICE has been regarded as de facto standard in circuit simulation.  Commercial releases of SPICE (e.g., PSPICE and HSPICE) typically contain a much larger selection of refined models.

B.Supmonchai Digital ICs SPICE Simulations 5 SPICE Decks  Writing a SPICE deck is like writing a good program  Plan  Plan: sketch schematic on paper or in editor  Modify existing decks whenever possible  Code  Code: strive for clarity  Start with name, , date, purpose  Generously comment  Test  Test:  Predict what results should be  Compare with actual  Garbage In, Garbage Out!

B.Supmonchai Digital ICs SPICE Simulations 6 SPICE Elements LetterElement RResistor CCapacitor LInductor KMutual Inductor VIndependent voltage source IIndependent current source MMOSFET DDiode QBipolar transistor WLossy transmission line XSubcircuit EVoltage-controlled voltage source GVoltage-controlled current source HCurrent-controlled voltage source FCurrent-controlled current source

B.Supmonchai Digital ICs SPICE Simulations 7 Units in SPICE LetterUnitMagnitude aatto ffemto ppico nnano umicro mmilli kkilo 10 3 xmega 10 6 ggiga 10 9 Ex: 100 femtofarad capacitor = 100fF, 100f, 100e-15

B.Supmonchai Digital ICs SPICE Simulations 8 Sources  DC Source Vdd vdd gnd 2.5  Piecewise Linear Source Vin in gnd pwl 0ps 0 100ps 0 150ps ps 1.8  Pulsed Source Vck clk gnd PULSE ps 100ps 100ps 300ps 800ps

B.Supmonchai Digital ICs SPICE Simulations 9 Example: RC Circuit * rc.sp * 2/2/03 * Find the response of RC circuit to rising input * * Parameters and models * option post * * Simulation netlist * Viningndpwl0ps 0 100ps 0 150ps ps 1.8 R1inout2k C1outgnd100f * * Stimulus * tran 20ps 800ps.plot v(in) v(out).end R1 = 2KΩ C1 = 100fF Vin + Vout -

B.Supmonchai Digital ICs SPICE Simulations 10 RC Circuit Result (Textual) legend: a: v(in) a: v(in) b: v(out) b: v(out) time v(in) time v(in) (ab ) m (ab ) m p p p p p p p p p p p m +b + + a p m +b + + a p b a p b a p b a p b a p b a p b a p b a p b a p b a p b a p b a p b a p b a p b a p b a p b a p b + + +a p b + + +a p b + + +a p b + + +a p b + + +a p b + + +a p b + +a p b + +a p b + +a p b + +a p b a p b a p b + +a p b + +a p b + +a p b + +a p b+ +a p b+ +a p b +a p b +a p b +a p b +a p b +a p b +a p b +a p b +a p b +a p b +a p b +a p b +a p b--+a p b--+a p b +a p b +a p b +a p b +a p b +a p b +a p b +a p b +a p b+a p b+a p b+a p b+a p b+a p b+a p b+a p b+a p ba p ba p ba p ba

B.Supmonchai Digital ICs SPICE Simulations 11 RC Circuit Result (Graphical)

B.Supmonchai Digital ICs SPICE Simulations 12 MOSFET Elements  M element for MOSFET M NMOD L=1U W=10U AD=120P PD=42U Mname drain gate source body type + W= L= + W= L= + AS= AD = + AS= AD = + PS= PD= + PS= PD=  Example: Node Name

B.Supmonchai Digital ICs SPICE Simulations 13 MOSFET Models  Earlier SPICE versions had three built-in MOSFET models:  LEVEL 1 (MOS1)  LEVEL 1 (MOS1) - Square law I-V characteristic  LEVEL 2 (MOS2)  LEVEL 2 (MOS2) - Detailed analytical MOSFET  LEVEL 3 (MOS3)  LEVEL 3 (MOS3) - Semi-empirical  MOS2 and MOS3 include second-order effects such as velocity saturation, mobility degradation, subthreshold conduction, and DIBL.  All three LEVELs do not provide good fits to the characteristics of modern devices.

B.Supmonchai Digital ICs SPICE Simulations 14 MOSFET Models (2)  For modern submicron devices, the Berkeley Short-Channel IGFET Model (BSIM) is the most widely used (commercially and academically).  BSIM version 1, 2, 3v3, and 4 are implemented as SPICE level 13, 39, 49, and 54, respectively  BSIM is a very elaborate model that are derived from the underlying device physics but use an enormous number of parameters to fit the behavior of modern transistor.  BSIM version 3v3 requires over 27 pages of over 100 parameters and device equations to describe the model.

B.Supmonchai Digital ICs SPICE Simulations 15 Selection of Models  The level (type) of MOSFET model to be used in a particular simulation can be specified through the.MODEL statement in SPICE.  With the statement, the user can describe a large number of model parameters including geometry of the device such as channel length and width. M NMOD L=1U W=10U AD=120P PD=42U MDEV PMOD L=1.2U W=20U.MODEL NMOD NMOS (LEVEL=1 VTO=1.4 KP=4.5E-5 CBD=5PF CBS=2PF).MODEL PMOD PMOS (VTO=-2 KP=3.0E-5 LAMBDA=0.02 GAMMA=0.4 + CBD=4PF CBS=2PF RD=5 RS=3 CGDO=1PF + CGSO=1PF CGBO=1PF)

B.Supmonchai Digital ICs SPICE Simulations 16 NMOS Transistor Circuit Model

B.Supmonchai Digital ICs SPICE Simulations 17 LEVEL 1 Model Equations  Corresponding to our unified model for manual analyses in the class.  Basic Current Models: where

B.Supmonchai Digital ICs SPICE Simulations 18 LEVEL 1 Model Equations (II) KP, VTO, GAMMA, PHI, and LAMBDA  Completely characterized by the five electrical parameters: k’, V T0, , |2  F |, and (KP, VTO, GAMMA, PHI, and LAMBDA in SPICE) TOX  Physical parameters, e.g., t ox (TOX) can be specified in stead of the electrical parameters. override  If both present simultaneously in the model, electrical parameters always override physical parameters.  Though grossly inaccurate, LEVEL 1 offers a quick, useful estimate of the circuits.

B.Supmonchai Digital ICs SPICE Simulations 19 LEVEL 2 and 3 Model Equations  Improved models for the drain current  Level 2: A number of semi-empirical corrections have been added to the basic equations.  Level 3: Majority of the model equations are empirical  Improving accuracy  Reducing complexity in calculation.  Although more accurate, LEVEL 2 and 3 models are still insufficient to achieve good agreement with experimental data for the deep submicron devices.

B.Supmonchai Digital ICs SPICE Simulations 20 Parasitic Capacitances  SPICE models use separate sets of equations in cut-off, linear, and saturation modes to calculate the device parasitic capacitances. C GB C GS C GD  Gate Capacitances: SPICE uses a simple model that represents the charge storage effect by three nonlinear two-terminal capacitors: C GB, C GS, and C GD (please see chapter 2 for the detail) TOXWL LD  Required geometry information: gate oxide thickness (TOX), channel width (W), channel length (L), and the lateral diffusion (LD).

B.Supmonchai Digital ICs SPICE Simulations 21 Parasitic Capacitances (2)  Junction Capacitance: SPICE uses the simple pn-junction model to simulate the parasitic capacitances of the source and drain diffusion regions. where AS and AD are the source and the drain areas; PS and PD are the source and the drain perimeters, respectively

B.Supmonchai Digital ICs SPICE Simulations 22 Parasitic Capacitances (3) CJ  C j is the zero-bias depletion capacitance per unit area at the bottom plate of the drain or the source diffusion region. (CJ in SPICE) CJSW  C jsw is the zero-bias depletion capacitance per unit length at the side-wall plate. (CJSW) MJMJSW  M j and M jsw are the junction degrading coefficients of the bottom and side-wall plates, respectively. (MJ, MJSW)  0.5 for abrupt juction and 0.33 for linearly graded junction  0 PB PHPPBSW   0 is the built-in junction potential which is actually a function of the doping densities (PB for bottom plate and PHP (MOS) or PBSW (BSIM) for side walls)

B.Supmonchai Digital ICs SPICE Simulations 23 Example: NMOS I-V Characteristics * mosiv.sp * * Parameters and models * include '../models/tsmc180/models.sp'.temp 70.option post * * Simulation netlist * *nmos Vgsggnd0 Vdsdgnd0 M1dggndgndNMOSW=0.36uL=0.18u * * Stimulus * dc Vds SWEEP Vgs end V gs V ds I ds 4/2

B.Supmonchai Digital ICs SPICE Simulations 24 Example: I-V Characteristics

B.Supmonchai Digital ICs SPICE Simulations 25 Example: Inverter Transient Analysis inv.spinv.sp * Parameters and models * param SUPPLY=1.8.option scale=90n.include '../models/tsmc180/models.sp'.temp 70.option post * Simulation netlist * Vddvddgnd'SUPPLY' VinagndPULSE0 'SUPPLY' 50ps 0ps 0ps 100ps 200ps M1yagndgndNMOSW=4L=2 + AS=20 PS=18 AD=20 PD=18 M2yavddvddPMOSW=8L=2 + AS=40 PS=26 AD=40 PD=26 * Stimulus * tran 1ps 200ps.end a y 4/2 8/2 **Unloaded inverter**

B.Supmonchai Digital ICs SPICE Simulations 26 Example: Inverter Transient Results Overshoot Very fast edges

B.Supmonchai Digital ICs SPICE Simulations 27 Subcircuits  Common elements can be declared as subcircuits  SPICE Decks are easier to read and maintain..subckt inv a y N=4 P=8 M1 y a gnd gnd NMOS W='N' L=2 + AS='N*5' PS='2*N+10' AD='N*5' PD='2*N+10' M2 y a vdd vdd PMOS W='P' L=2 + AS='P*5' PS='2*P+10' AD='P*5' PD='2*P+10'.ends  Ex: Fanout-of-4 Inverter Delay  Reuse inv  Shaping  Loading

B.Supmonchai Digital ICs SPICE Simulations 28 Example: FO4 Inverter Delay * fo4.sp * Parameters and models * param SUPPLY=1.8.param H=4.option scale=90n.include '../models/tsmc180/models.sp'.temp 70.option post * Subcircuits * global vdd gnd.include '../lib/inv.sp' * Simulation netlist * Vddvddgnd'SUPPLY' VinagndPULSE0 'SUPPLY' 0ps 100ps 100ps 500ps 1000ps X1abinv * shape input waveform X2bcinvM='H' * reshape input waveform

B.Supmonchai Digital ICs SPICE Simulations 29 Example: FO4 Inverter Delay (2) X3cdinvM='H**2' * device under test X4deinvM='H**3' * load x5efinvM='H**4' * load on load * Stimulus * tran 1ps 1000ps.measure tpdr* rising prop delay + TRIG v(c)VAL='SUPPLY/2' FALL=1 + TARG v(d) VAL='SUPPLY/2' RISE=1.measure tpdf* falling prop delay + TRIG v(c) VAL='SUPPLY/2' RISE=1 + TARG v(d) VAL='SUPPLY/2' FALL=1.measure tpd param='(tpdr+tpdf)/2'* average prop delay.measure trise* rise time +TRIG v(d)VAL='0.2*SUPPLY' RISE=1 +TARG v(d)VAL='0.8*SUPPLY' RISE=1.measure tfall* fall time +TRIG v(d)VAL='0.8*SUPPLY' FALL=1 +TARG v(d)VAL='0.2*SUPPLY' FALL=1.end

B.Supmonchai Digital ICs SPICE Simulations 30 Example: FO4 Inverter Delay Results

B.Supmonchai Digital ICs SPICE Simulations 31 Device Characterization  Modern SPICE models are so complicated that the designer cannot easily read key performance characteristics from the model files.  A more convenient approach is to run a set of simulations and then extract parameters and other interesting data, e.g., I-V characteristics, threshold voltage, effective resistance and capacitance.  Various methods to find these parameters and the required simulations are described in the literature.

B.Supmonchai Digital ICs SPICE Simulations 32 Device Characteristics Comparison

B.Supmonchai Digital ICs SPICE Simulations 33 Pitfalls and Fallacies  Failing to estimate diffusion and interconnect parasitics in simulations  Diffusion capacitance can account for more than 50% of the delay of a high fan-in, low fanout gate. Make sure that the area and perimeter of the source and drain are included in the simulation.  RC delay of the long wires dominate the path delay but it is difficult to estimate.  Good models describe not only the circuit but also the input edge rates, the output loading, and parasitics such as diffusion capacitance and interconnect.  Gate delay is strongly dependent on the rise/fall time of the input and even more strongly on the output loading

B.Supmonchai Digital ICs SPICE Simulations 34 Pitfalls and Fallicies (2)  SPICE is prone to Garbage in, Garbage out! So do not blindly trust the results from SPICE.  Failing to account for hidden scale factors  Identifying incorrect critical path  Choosing inappropriate transistor sizes  Compare results of a design with carefully selected transistor sizes to a convention design with poorly selected sizes.  Do not use SPICE in place of thinking  Do not use SPICE too much. Circuit simulation should be guided by analysis

B.Supmonchai Digital ICs SPICE Simulations 35 Pitfalls and Fallacies (3)  Rule of Thumbs: “Assume SPICE decks are buggy until proven otherwise.”  If the simulation does not agree with your expectations, look closely for errors or inadequate modeling in the deck.  Motto: Check and Recheck!