1 5. Application Examples 5.1. Programmable compensation for analog circuits (Optimal tuning) 5.2. Programmable delays in high-speed digital circuits (Clock skew compensation) 5.3. Automated discovery – Invention by Genetic Programming (Creative Design) 5.4. EDA Tools, analog circuit design 5.5. Adaptation to extreme temperature electronics (Survivability by EHW) 5.6. Fault-tolerance and fault-recovery 5.7. Evolvable antennas (In-field adaptation to changing environment) 5.8. Adaptive filters (Function change as result of mission change) 5.9 Evolution of controllers

2 Fault-tolerance and fault-recovery Fault tolerance is a very important requirement for electronic systems that operate in harsh environments, where the replacement of faulty components may take too much time or even be completely impossible. A typical example comes form the area of space exploration, where electronic circuits must “survive” in unknown environments.

3 Motivation: Space applications Despite the technological progress, still until now expensive spacecrafts have been lost or impaired by single events that escaped detection prior to launch. Historically, redundancy has been a central method of achieving resistance to failure. A 1994 JPL study of the critical telecommunication system on six prior missions (Voyager 1 and 2, Viking 1 and 2, Galileo, and Magellan) revealed that redundancy is likely to have saved five of these missions from catastrophic failure. But redundancy is costly in terms of the resources that must be devoted to backup systems. JPL work concentrates on events caused by the space environment because design and environment causes continue to be the most significant sources of failure, in spite of the improvement in design techniques and the use of more refined environmental models. Our mission is to design and develop electronic components and systems that are inherently insensitive to faults by using on-board evolution in hardware to achieve fault-tolerant and highly reliable systems

4 EWH and Fault Tolerance –redundancy: large number of transistors –fault detection and annunciation: constant evaluation of the circuit –on-line self-repaired: swapping circuit configuration by searching in the population or by running the GA during a limited number of generation. Explicit or Fitness Based Fault Tolerance: The fitness evaluation function assesses the circuit behavior without faults and in the presence of faults known a-priori. The best individual adequately perform the task in the presence of known faults (Layzell, Keymeulen); Implicit or Population Fault-Tolerance: The fitness evaluation function assesses the circuit behavior only without faults. The population of evolved circuits contain individual (mutant) which adequately performs a task in the presence of a fault unknown a-priori that renders the previously best individual useless (Thompson, Layzell, Keymeulen);

5 Self-Recovery After a fault is applied and detected (drop in the fitness value), the following procedure for self-recovery is undertaken: Look for a mutant that scores satisfactorily under the particular fault; If no satisfactory mutant is found, re-start evolution under faulty condition to achieve better individual → Evolution “explores” fault component to achieve desired behavior;

6 Fitness Based Fault Tolerant Thompson (1996) demonstrated the general concept of fault tolerance through evolutionary experiments by evolving the contents of a RAM that controls a robot in a wall avoidance task. The RAM consisted of 32 bits that could be mapped in a straightforward way using binary chromosomes. After 85 generations a solution to this task was achieved, and 32 faults were applied to the best individual by respectively switching each of its 32 bits. The worst fault, the one that most deteriorated the individual’s performance, was selected. Another generation was performed with the worst fault being applied to all individuals during the fitness evaluation function. A new “worst fault” was determined for the best individual of this generation, and applied subsequently in the next generation. The process was then repeated each generation. At generation 204 an individual that was tolerant to all the 32 possible faults was achieved.

7 Population Based Fault Tolerant Layzell(1999) Hardware evolution of oscillators using the evolvable motherboard; Circuit components: bipolar transistors; Faults: removing the component from the circuit, i.e., a faulty component is modeled by an open-circuit The basic strategy to evaluate fault tolerance consisted of removing each transistor (individually) from the best circuit achieved by evolution. Three situations may then occur: (1) the best individual continues to work normally without the removed component; (2) the best individual and all the other individuals of the population do not work after the component is removed; (3) the best individual does not work, but another individual in the population does work properly when the component is removed. The third situation characterizes PFT. After 20 runs of the oscillator experiment, Layzell and Thompson observed many cases in which PFT was taking place.

8 JPL work in evolutionary fault-recovery Demonstrate evolution-enabled fault-tolerance on reconfigurable hardware Uses FPTA for transistor level control Examples of repaired circuits –Logical circuit (XNOR) –Computational circuit (Gaussian and Multiplier) –Signal Processing circuit (Data Converter - 4bit DAC)

9 Self-healing of a Gaussian Circuit 2 cells of FPTA-0 (88 bits) –5 Connections between 2 cells: solution after 200 generations –Cut 1 connection after 440 generations. –Start the GA and recover a desired circuit after 60 generations Fault Application Fault Application Self-repaired Individual Generations Output[V] Input[V] Generations Fitness

10 Population Fault-Tolerance for XNOR Gate Evolution of XNOR Circuit using FPTA-0: –Two FPTA cells were cascaded; –Six faults that were applied to the best circuit, by opening (fault 1, fault 2, and fault 4) or closing (fault 0, fault 3, and fault 6) six switches. Both implicit and explicit fault-tolerance experiments performed; The implicit technique based on the population dynamics outperformed the explicit technique, based on the fitness evaluation function.

11 (Left) Response of the best circuit configuration obtained by evolution when six faults are injected. (Right) Response of mutants found in the population performing the best for each fault. Further evolution was needed to find a XNOR circuit for fault 3 and fault 4 Experiments on Fault Tolerance (XNOR Gate)

12 Multiplier with two cascaded FPTAs (88 bits) 6 external connections between 2 PTAs Find solution after 59 generations Cut 1 external connection after 60 generations. Start the GA and recover a desired circuit after 20 generations Self-Repair of Multiplier Circuits

13 Best individual at generation 59 Fault injected at generation 60 Self-repaired individual at generation 80 FPTA design for Fault-tolerant multiplier with 6 injected faults Generations Fitness Self-repair of Multiplier Circuits

14 Hardware experiments using FPTA-2 chip; Evolve first a 2-bit DAC, using it as a building block to evolve a 3-bit DAC, and reusing it to evolve a 4-bit DAC. Total number of FPTA cells: 20 –4 cells mapping a previously evolved 3-bit DAC (evolved from a 2-bit DAC); –4 cells mapping human designed Operational Amplifier (buffering and amplification); –12 cells have their switches’ states controlled by evolution. Fault application: open all the switches of 2 cells of the evolved circuit; Self-repair of Digital to Analog Converters

15 Faulty Cells (Black): All switches opened (stuck-at 0 fault); 3-bit DAC Cell: Cells ‘0’, ‘1’, ‘2’ and ‘3’ map the previously evolved 3-bit DAC, whose output is O3. OpAmp Cell (Label ‘A’): constrained to OpAmp implementation Evolved Cell (Grey): switches’ states controlled by evolution. O4 is the output of the 4-bit DAC. Self-repair of Digital to Analog Converters

16 Fault-Tolerant data converter (4bit DAC): responses Response of Best Evolved CircuitResponse of deteriorated circuit Response of recovered circuit Recovery by Evolution of 4bit DAC: 12 Cells used by evolution 2 Cell constrained to OpAmp 4 Cells constrained to 3bit DAC 2 Faulty Cells Input:10 kHz – Sampling: 20 kHz Full-Scale Output Voltage: 0.6 Volt