Dr Renato Turchetta CMOS Sensor Design Group CCLRC Technology Large Area Monolithic Active Pixel Sensors

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, Outline  Introduction on CMOS MAPS  Large sensors for imaging  The INMAPS process  CALICE  Conclusions

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, CMOS Monolithic Active Pixel Sensor (MAPS) Advantages  Standard CMOS technology  all-in-one detector-connection- readout = Monolithic  small size / greater integration  low power consumption  radiation resistance  system-level cost  Increased functionality  increased speed (column- or pixel- parallel processing)  random access (Region-of-Interest ROI readout) Column-parallel ADCs Data processing / Output stage Readout control I2C contro l

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, CMOS sensors in digital cameras Consumer/prosumer Digital cameras Digital intraoral imaging Digital mammography Mobile phones Web cams

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, Metal layers Polysilicon P-WellN-WellP-Well N+ P+N+ CMOS sensors for radiation detectors Dielectric for insulation and passivation Silicon band-gap of 1.1 eV  cut- off at 1100 nm. Good efficiency up to ‘low’ energy X-rays. For higher energy (or neutrons), add scintillator or other material. Need removal of substrate for detection of UV, low energy electrons. Photons Charged particles 100% efficiency. Radiation P-substrate (~100s  m thick) P-epitaxial layer (up to to 20  m thick) Potential barriers R. Turchetta et al., NIM A 458 (2001)

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, Outline  Introduction on CMOS MAPS  Large sensors for imaging  The INMAPS process  CALICE  Conclusions

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, CMOS RAL First test structure designed in First large sensor (camera-on-a-chip for tracking stars) designed in 2000 Over 30 years cumulated design experience. 1 st time right design. CMOS Sensor design group established in 2006 Design with many CMOS technologies, down to 0.18  m feature size. Note that: scaling for image sensor < mixed mode < digital Design for Space science, Earth Observation, Particle Physics, Biology, Medicine, … Detecting: Photons: visible, UV, EUV, X-ray (with scintillators), … Charged particles: MIPs, low/medium energy electrons (few keV up to 1 MeV) Voltages !

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, CMOS RAL. ESA Solar Orbiter 12 Mpixel (4kx3k) sensor for ESA Solar Orbiter CMOS CIS 0.25  m, 8  m epi, 5  m pixel pitch, Bacthinning down to epi layer (supported silicon), backilluminated Backthinning down to 100  m demonstrated on a 2x2cm 1.4Mpixel sensor. 50 and 35  m thick sensor to be tested Front-illuminatedBack-illuminated Back-illuminated image was taken through a 50nm filter at 350nm with IR-blocking filter.h Courtesy of N. Waltham (RAL-SSTD)

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, ½ D sensor designed for X-ray medical imaging. I-ImaS consortium, EU funded and led by prof R. Speller (UCL) CMOS CIS 0.35  m, 14  m epi, 32  m pixel pitch 512*32 pixels at 32  m pitch plus 4 rows and columns on both sides for edge effects 14 bit digital output; one 14- bit SAR ADC every 32 channel 20 MHz internal clock; 40 MHz digital data rate CMOS RAL. X-ray imaging

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, CMOS RAL. Fast sensor Designed within the UK-MI3 consortium ( aiming at developing novel CMOS APS. Led by prof N. Allinson (Sheffield Univesity) CMOS CIS 0.35  m, 14 and 20  m epi, 25  m pixel pitch Backthinned down to the epi Format 512x512 + black pixels (520x520 full format) 3T pixel with flushed reset Noise < 25 e- rms Full well capacity > 10 5 e- On-chip SAR ADCs, one for 4 columns. Selectable resolution: 10 or 12. Adjustable range. Region of interest readout. Total flexibility. Example: 20 thousands frames per second for six 6x6 regions of interest

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, Radiation hardness. Electronics Transistors. Threshold shift: reduces with shrinking feature size Bird’s beak effect: use enclosed geometry transistors Transistor leakage current: use guard-rings to separate transistors ~t ox micron

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, Radiation hardness. Sensors Diodes. Radiation damage increases leakage current Charge collection is mainly by diffusion Radiation damage reduces minority carrier lifetime  diffusion distance is reduced This latter is going to be the ultimate limit, unless an electric field is added So thickness of epi not so important after irradiation Distance of diodes can be important Surface damage can be important Depends on details of technology and layout.

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, Single pixel S/N dependence on impact point No rad No rad Device simulation. 4-diode 15  m pixel Less variation in S/N varies over pixel before and after irradiation. S at edges still usable after p/cm 2. Device simulation. Single diode 15  m pixel

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, Irradiation with hadrons S/N Dose (log 10 (p/cm2)) S/N Dose (log 10 (p/cm2)) Calculations/simulations/experiments indicate O(10 14 p/cm 2) as the limit for reasonable (a few 100s e-) charge collection. Limits can move further as noise goes down (~e- rms noise looks achievable) Results depend on design detail (surface effects can be dominant) and technology Results from a test sensor in CIS 0.25  m technology. 128x384 pixels, 15  m pitch

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, Large area sensors Reticle. Size limited to ~ 2 cm. Reticle is stepped-and repeated  gaps between reticles CCD foundry. Sometimes large chips are required  different programming of stepping to have no gap  ‘stitching’ CMOS sensor market Driven by design of CMOS sensors as replacement of 35 mm film. At a few foundries, it is now possible to design stitched (seamless) sensors  ‘wafer- scale’ Foundry choice rapidly widening 6x6 cm sensor for medical imaging to manufacturing in May/June 2007

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, Outline  Introduction on CMOS MAPS  Large sensors for imaging  The INMAPS process  CALICE  Conclusions

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, How much CMOS in a CMOS Sensors Pixel? NMOS P-WellN-WellP-Well N+ P-substrate (~100s  m thick) N+ N-Well P+ Diode NMOS PMOS 100 % efficiency  only NMOS in pixel  no complicated electronics Complicated electronics  NMOS and PMOS,i.e. CMOS  low efficiency

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, The INMAPS process NMOS P-Well N+ P-substrate (~100s  m thick) N+ N-Well P+ Diode NMOS PMOS Deep P-Well N-Well Deep N-Well Standard CMOS with additional deep P-well implant. Quadruple well technology 100% efficiency and CMOS electronics in the pixel. Optimise charge collection and readout electronics separately! RAL development, driven by ILC (P. Dauncey et al.)

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, Outline  Introduction on CMOS MAPS  Large sensors for imaging  The INMAPS process  CALICE  Conclusions

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, CALICE design Sensor for the ECAL for ILC (International Collider) Main requirements Pixel size 50  m Time beam crossing rate (150 ns) Total detector: pixels In-pixel Sparse readout Technology INMAPS 0.18  m 6 metal levels, linear capacitors, high-value resistors Choice of diodes, including pinned diodes Stiching up to wafer scale (200 mm diameter) Choice of epi: 5 and 12  m for first prototype than up to 20  m

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, The pixels schematic Rst Vrst Preamp PreRst Buffer s.f Cfb Cin Buffer s.f Vth+ Vth- Reset Sample Cstore --ns Preamp Shaper Rst Cpre Cfb Rfb Rin Cin Vth+ Vth- Pre-Shaper Pre-Sampler Analogue front-end Low gain differential amplifier Two pixel architectures, each with two variants. Not shown, but still in the pixel:  Comparator with 4-bit threshold trimming and mask bit  Logic for self-reset  Memory for 4-bit trimming and mask

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, Pre-sample Pixel layout Analogue front-end Memory for 4-bit trimming and mask Comparator with 4- bit threshold trimming and mask Pre-shaper layout is similar. 50  m pitch and over 200 transistors per pixel Logic for self-reset Low-gain diff amp 4 diodes

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, The sensor floorplan (V1.0) Pre-Sample Architecture Pre-Shaper Architecture Sensor is about 1cmx1cm 8 units of 42x84 pixels 2 units per pixel type Each unit has a 5-pixel wide for logic control and hit buffering Buffer for 19 hits per row 13-bit time stamp Configuration registers 6 million transistors in total Pixel V1 Pixel V2

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, Device simulation Bias: n-Well 1.8/1V Diodes: 1.5V Diodes Adjacent Diodes Electronics Substrate (left floating) Epi-Layer

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, Simulation Setup 7 Hit Points simulated 1 µm distance

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, Charge Collection Main parameter to vary is Diode SizeILC Bunch spacing ~ 300 ns Simulation for 12  m epi layer thickness Signal to Noise > 15 for 1.8 µm Diode Size (implemented in design) over the entire surface of the pixel  100% efficiency

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, Outline  Introduction on CMOS MAPS  Large sensors for imaging  The INMAPS process  CALICE  Conclusions

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, Conclusions Several large (reticle size) MAPS designed by RAL Pitch down to 5  m Epi up to 20  m Pixels up to 12 million Sensors with analogue output, on-chip ADCs, control electronics Backthinning: demonstrated on 100  m thickness; 50 and 35  m to be tested Radiation hardness; up to p/cm 2 on a 0.25  m CIS sensor, but depending on technology and layout details Large 6x6 cm sensor to be taped-out in May/June this year INMAPS process: full CMOS in the pixel AND 100% efficiency; wafer-scale sensor is possible Design for CALICE in INMAPS 0.18  m First 1x1cm prototype to manufacturing this week Second sensor next year: stitching is available Another test sensor (low noise pixels) to be taped-out in June plus one more in next 12 months

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, Acknowledgements CALICE UK: P. Dauncey, J.A. Ballin, A.-M. Magnan, M. Noy (Imperial College London), J.P. Crooks, M. Stanitzki, K.D. Stefanov, M. Tyndel, E.G. Villani (Rutherford Appleton Laboratory), Y. Mikami, O. Miller, V. Rajovic, N.K. Watson, J.A. Wilson (University of Birmingham) MI3: N. Allinson (Sheffield) plus everyone else from Sheffield, UCL, Liverpool, Glasgow, Brunel, LMB-MRC Cambridge, York, Surrey, Institute of Cancer Research-Royal Marsden Hospital and RAL I-ImaS: R. Speller (UCL) plus everyone else from UCL, Imperial College, University of Trieste (Italy), University of Ioannina, CTI, ANCO (Greece), ACTA (Netherlands), SINTEF (Norway) and RAL

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, Noise Occupancy Noise for 2880 bunches With Noise=O(10 -6 )  P=0.3 % for 1 hit per pixel  P= % for 2 hit per pixel But O(10 12 ) pixels !  ~ single hits  ~ double hits  ~0 triple hits Per Row (42 pixels) 0.15 Hits

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, MAPS DAQ & Testing Development of DAQ board and firmware has started Complete test setup foreseen –Cosmics –Sources –Laser –Test beam

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, RAL Laser Test setup Powerful Laser setup 1064, 532 and 355 nm Wavelength Accurate focusing (<2 µm at longest wavelength) Pulse Width 4 ns 50 Hz Repetition rate Fully automatized Will be used to test the MAPS

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, Simulation Chain Event Generation e.g. Pythia Event Generation e.g. Pythia Detector Simulation MOKKA Detector Simulation MOKKA MAPS Digitizer as MARLIN processor LCIO Detector Simulation SLIC LCIO

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, Mokka Detector Simulation Implementation of the MAPS into MOKKA –Patched MOKKA x50 µm pixel size 15 µm “Active Area” (Epi-layer) Detector Model used LDC01(Sc) ECAL with 30 layers –20 layers 2.1 mm Tungsten –10 layers 4.2 mm Tungsten Charge diffusion and thresholds are implemented in a separate “Digitization” step

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, Running with SLIC MAPS 50 μm  50 μm p

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, Beam background Done using GuineaPIG Trying to estimate beam induced background in the ECAL Testing two scenarios –500 GeV Baseline –1 TeV High Lum 1 TeV High Lum is “worst-case” scenario

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, TeV High Luminosity “Ring of Fire” for small ECAL Radii

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, Beam Background Occupancy MAPS Reset time

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, ILC configurations

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, CMOS Image Sensor Technology. 1 In general, any CMOS process have different flavours. The basic one is digital. Then MixedMode/RF, High Voltage, …, CIS (CMOS Image Sensor). Transistors don’t change. Modules added: high value resistors, linear capacitors, … For CIS: one/two masks/implants added to improve image quality / reduce leakage current

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, CMOS Image Sensor Technology. 2 Masks for colour filters, microlenses. Special BEOL for improved oxide transmission Stitching for sensors larger than reticle is becoming more common due to push for 35mm film replacement 0.18  m available, 0.13  m starting this year in different places. Pixel transistors still at 0.35  m equivalent Epitaxial wafers are generally used: better quality, reduced cross-talk Thickness: depends on foundry, generally up to 20  m thick epi layer

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, The sensor unit (V1.0) Consists of 42x84 pixels Has a logic strip for –5 pixels wide –Hit buffering using SRAM technology, 19 Hits per Row –Time stamping (13 bit) –Configuration registers –the only part with Clock lines Logic strip is a “dead area” for particle detection (~ 11 % inefficiency) Pixels Logic Strip 42 pixels 5 pixels 84 pixels

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, Data format A row of 42 pixels is split into 7 groups of 6 pixels each (“patterns”) The logic writes the following data format for each row –Time stamp (13 bits) –pattern number (3bits) –pattern (6 Bits) 1 Hit = 22 Bits On top :Row Enconding (9 Bits) 1 Hit = 31 Bit altogether

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, Sensor Simulation We are using Centaurus TCAD to simulate the sensor Using CADENCE GDS file for pixel description Simulate diodes from adjacent pixels for charge sharing effects Detailed Pixel performance studies –Collection Efficiency –Charge Collection Time –Signal/Noise

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, Signal/Noise *N.B. S/N 0.9µm N = 16 e - *N.B. S/N 1.8µm N = 16.5 e - *N.B. S/N 3.6µm N = 21.3 e - Signal to Noise > 15 for 1.8 µm Diode Size Some uncertainty for the absolute Noise levels, due to simulation imperfections Critical Measurement with the real sensor

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, The ECAL MAPS Pixel Size (50 x 50 µm) Binary Readout (1 bit ADC realized as Comparator) 4 Diodes for Charge Collection Time Stamping with 13 bits (8192 bunches) Hit buffering for entire bunch train Capability to mask individual pixels Threshold adjustment for each pixel For the MAPS ECAL a specific MAPS was designed:

Workshop on Silicon Detector Systems for the CBM experiment GSI Darmstadt, April 18-20, Sensor Electronics Two types of pixel readout Shaper & Sample Deadtime (~600 ns/ 450 ns ) Simulation shows similar noise characteristics Both share the Comparator design and everything downstream Having two front-end architectures allows us to explore several ideas at once