Presenter: Jyun-Yan Li A software-based self-test methodology for in-system testing of processor cache tag arrays G. Theodorou, N. Kranitis, A. Paschalis Department of Informatics & Telecommunications, University of Athens, Greece D. Gizopoulos Department of Informatics, University of Piraeus, Greece On-Line Testing Symposium (IOLTS), 2010 IEEE 16th International

Software-Based Self-Test (SBST) has emerged as an effective alternative for processor manufacturing and in- system testing. For small memory arrays that lack BIST circuitry such as cache tag arrays, SBST can be a flexible and low-cost solution for March test application and thus a viable supplement to hardware approaches. In this paper, a generic SBST program development methodology is proposed for periodic in-system (on-line) testing of L1 data and instruction cache memory tag arrays (both for direct mapped and set associative organization) based on contemporary March test algorithms. The proposed SBST methodology utilizes existing special performance instructions and performance monitoring mechanisms of modern processors to overcome cache tag testability challenges. 2

Experimental results on OpenRISC 1200 processor core demonstrate that high test quality of contemporary March test algorithms is preserved while low-cost in-system testing in terms of test duration and test code size is achieved. 3

Memory Built-In Self-Test(MBIST)  at-speed and several tests  Impact on chip area and performance  SBST has non-intrusive and flexibility Defect tag arrays may cause erroneous cache miss  No MBIST circuit because size 4

Performance counter [16] Performance counter [16] This paper March SS [2] March SS [2] Direct mapped D$ SBST [14] Direct mapped D$ SBST [14] Implement SBST 5 MBIST [5] MBIST [5] compare March Memory fault simulator Simulation engine & fault descriptors Traditional March [1] Traditional March [1] March Minimal SS [3] March Minimal SS [3] RAMSES [19] RAMSES [19] Impact on chip area & performance Detect erroneous cache miss SBST

March SS Data cache algorithm  Create_address(DB:i:B) Instruction cache algorithm  Create_address(DB:i:0) 6 r0(1): read data (inverted data) B: word offset DB: N-bit word B: word offset DB: N-bit word Fetch first instruction in the cache line for alignment TF RDF

7 start create address (A) Prefetch block(A) create address (A) i=Nd? M2, M3,M4, M5 Load(A) Prefetch block(A) i=Nd? Performan ce counter =0? No Yes error No Test successful Yes R hit W tag Load(A) R hit K times? Yes end Yes No R hit W tag M0 M1

8 start create address (A) Prefetch block(A) i=Nd? W tag M0 Disable cache create address (A) M1 Call (A) Prefetch block(A) M2, M3,M4, M5 Performan ce counter =0? error No Test successful K times? end Yes No Enable cache Disable cache Call (A) Enable cache Disable cache Yes No i=Nd? No Yes R hit

OpenRISC 1200 Result: 9 typeWrite policyTag array cache4Kbyte direct mappedWrite through256*20 [15] n: total number of bits of the array

Write operation  [14]: 6 instructions  This paper: 2 instructions Read verification  [14]: 7 instructions  This paper: 2 instructions March C- algorithm 10

Using March SS algorithm and decreasing code size by performance counter and prefetch instruction My comment  Assume cache hit to detect cache behaviors by prefetch operation  Some jargons not describe, ex: CF  Fault description’s definition 。 some March tests do not guarantee complete fault coverage in all fault models 11