Lecture #3 Page 1 ECE 4110– Sequential Logic Design Lecture #3 Agenda 1.FPGA's 2.Lab Setup Announcements 1.No Class Monday, Labor Day Holiday 2.HW#2 assigned

Lecture #3 Page 2 Digital Design Flow Designing Large Circuits - this is the ideal process

Lecture #3 Page 3 Digital Design Flow Designing Large Circuits - this is reality

Lecture #3 Page 4 FPGA's What is an FPGA Field Programmable Gate Array An FPGA uses Re-configurable Logic Blocks - we set the config bits of this block to set its Boolean logic function - the configuration is a Truth Table (or Look Up Table) of functionality Out In1 In2 config config Out 000 NOT(In1) 001 NOT(In2) 010 OR 011 NOR 100 AND 101 NAND 110 XOR 111 XNOR

Lecture #3 Page 5 FPGA's LUTs = Look Up Tables - we can program the LUTs to be whatever type of gate is needed by the design - there are a finite number of LUTs within a given FPGA (also called "resources") The LUTs are configured into an ARRAY on the silicon - Array of LUT's = Array of Gates = Gate Array Out In1 In2 config Out In1 In2 config Out In1 In2 config Out In1 In2 config Out In1 In2 config Out In1 In2 config Out In1 In2 config Out In1 In2 config Out In1 In2 config

Lecture #3 Page 6 FPGA's Programmable Interconnect - there are programmable interconnect switches that connect the LUTs LUT X X X X X X X X X X X X XXX XX

Lecture #3 Page 7 FPGA's Configuration - We start with a Gate Level Schematic of our design (from synthesis) - The FPGA LUTs are configured to implement Gates LUT X X X X X X X X X X X X XXX XX

Lecture #3 Page 8 FPGA's Configuration - The interconnect switches are then programmed to implement the net connections LUT INVORLUTINVANDLUT X X X X X X X X X X X X XXX XX A B C Out

Lecture #3 Page 9 FPGA's Configuration - The LUT and Interconnect configuration is volatile (i.e., it goes away when power is removed) - Since the programming is done by the user after fabrication, we call it "Field Programmable" - We now understand where Field Programmable Gate Array LUT INVORLUTINVANDLUT X X X X X X X X X X X X XXX XX A B C Out

Lecture #3 Page 10 FPGA's Adding More Functionality - FPGA manufacturer's quickly learned that Flip-Flops would be useful - They put a DFF next to a 4-Input LUT to form a "Configurable Logic Block" (CLB), –CLB also known as Logic Element (LE) CLB X X X XX

Lecture #3 Page 11 FPGA's Adding Even More Functionality - To Improve performance, common logic functions were "hard coded" on the silicon - Block RAM - Adders / Multipliers - Global Clock Buffers - even Microprocessors!

Lecture #3 Page 12 FPGA's What else can we program? - Which Pins to use on the package - What logic levels - CMOS_33, CMOS25 - SSTL, SSTL2, etc…

Lecture #3 Page 13 Lab Setup We will use the Altera DE2 FPGA board (found in the CAD Lab) One of the major boards in learning about digital logic, computer organization, and FPGAs. Featuring an Altera Cyclone TM II FPGA. FPGA Part Numbers –Cyclone II EP2C35F672C6 On-board jumper settings –33,000 Logic Elements (LE), which is equivalent to about 1M gates –LEDs, Switches, Seven-Segments, PS/2 mouse or keyboard, USB device, Ethernet, audio ports, video port –50 and 27 MHz oscillators, with option to external SMA clock –Flash programmable to hold FPGA program –2 expansion ports –(user's guide on website)

Lecture #3 Page 14 Lab Setup Programming the FPGA - Boundary Scan (JTAG) - a daisy chain protocol that allows programming of chips - FPGA - we can program the FPGA direction - volatile nature means if we remove power, we'll loose program - EEprom - we can download our code into an on-board EEprom - Upon power up, the EEprom will program the FPGA NOTE: We'll mostly program the FPGA directly

Lecture #3 Page 15 Lab Setup Programming the FPGA For DE2: Compile the top-level project for the appropriate Cyclone II EP2C35F672C6 –Turn on the red power button for the DE2 board only when used. Keep the power cord connected. –Open the Programmer from the Quartus Tools menu or click the Programmer icon. –If it is not already setup, click Hardware Setup and Add the USB blaster. Click Close. –Check that the proper File and Device are already listed. If not, click AddFile and select the proper file. –Check that the Program and Verify boxes are checked next to the file name. –Click the Start button to download the project configuration data into the Max or Flex device. –After several seconds, the Programmer should indicate success. –The Altera board is now running your project on the DE2 board. On the UP1/UP2 board: –For Max, set all four jumpers (TDI, TDO, DEVICE, BOARD) to the up position. –For Flex, set the first two jumpers (TDI, TDO) to the down position and the last two jumpers (DEVICE, BOARD) to the up position. –Open the top-level design project in Quartus. –Open the Programmer from the Quartus Tools menu or click the Programmer icon. – If it is not already setup, click Hardware Setup and Add the Byteblaster on LPT1. Click Close. –The Mode should say JTAG. –Check that the proper File and Device are already listed. If not, click AddFile and select the proper file. –Check that the Program and Verify boxes are checked next to the file name. –Click the Start button to download the project configuration data into the Max or Flex device. –After several seconds, the Programmer should indicate success. –The Altera board is now running your project on the UP1/UP2 board.

Lecture #3 Page 16 Lab Setup Misc - We will design mainly in VHDL, although Design tools allow schematic entry - We can design, compile, simulate in either 1) ModelSim 2) Xilinx ISE 3) Altera Quartus II - We will synthesize, PAR, Verify, and Download in Quartus II

Lecture #3 Page 17 FPGA Overview The Real World - FPGA's historically (mid 90's) have been too expensive for deployment in commercial designs - ASICs have become very expensive and FPGA's have become more powerful - As a result, it is now cost effective to use FPGA's in designs - Learning how an FPGA operates and how to get performance out of them is a highly sought after engineer skill! Now there is the HardCopy ASIC compatible FPGA. –It costs much less (per product), and performs a lot faster than traditional FPGA. –Transition to ASIC this way can take only 6 weeks. –Catch is??