1HSSPG Georgia Tech High Speed Image Acquisition System for Focal-Plane-Arrays Doctoral Dissertation Presentation by Youngjoong Joo School of Electrical.

Slides:



Advertisements
Similar presentations
Controller Tests Stephen Kaye Controller Test Motivation Testing the controller before the next generation helps to shake out any remaining.
Advertisements

Georgia Tech Digital Back-end µHRG interface Curtis Mayberry School of Electrical and Computer Engineering Georgia Institute of Technology January 13 th,
Lecture 17: Analog to Digital Converters Lecturers: Professor John Devlin Mr Robert Ross.
Sensors Interfacing.
ECE 353 Introduction to Microprocessor Systems Michael G. Morrow, P.E. Week 14.
Data Acquisition Risanuri Hidayat.
ECE 353 Introduction to Microprocessor Systems Michael G. Morrow, P.E. Week 14.
Oscilloscope Watch Teardown. Agenda History and General overview Hardware design: – Block diagram and general overview – Choice of the microcontroller.
The Design of a Delta Sigma Modulator Presented by: Sameh Assem Ibrahim 24-July-2003.
Mixed Signal Chip Design Lab Analog-to-Digital Converters Jaehyun Lim, Kyusun Choi Department of Computer Science and Engineering The Pennsylvania State.
Pixel-level delta-sigma ADC with optimized area and power for vertically-integrated image sensors 1 Alireza Mahmoodi and Dileepan Joseph University of.
1 Analog-to-digital converter Prepared by: Selah al-Battah Mohammed Al-khabbaz Atiyah Alnakhli Ali Dumyati.
Design and Implementation a 8 bits Pipeline Analog to Digital Converter in The Technology 0.6 μm CMOS Process Eri Prasetyo.
RMO4C-2 A Low-Noise 40-GS/s Continuous-Time Bandpass ΔΣ ADC Centered at 2 GHz Theo Chalvatzis and Sorin P. Voinigescu The Edward S. Rogers Sr. Department.
Current-Mode Multi-Channel Integrating ADC Electrical Engineering and Computer Science Advisor: Dr. Benjamin J. Blalock Neena Nambiar 16 st April 2009.
1 Dr. Un-ki Yang Particle Physics Group or Shuster 5.15 Amplifiers and Feedback: 3.
Real time DSP Professors: Eng. Julian S. Bruno Eng. Jerónimo F. Atencio Sr. Lucio Martinez.
A scalable DAQ system using the DRS4 sampling chip H.Friederich 1, G.Davatz 1, U.Hartmann 2, A.Howard 1, H.Meyer 1, D.Murer 1, S.Ritt 2, N.Schlumpf 2 1.
Analog-to-Digital Converters Prepared by: Mohammed Al-Ghamdi, Mohammed Al-Alawi,
Why prefer CMOS over CCD? CMOS detector is radiation resistant Fast switching cycle Low power dissipation Light weight with high device density Issues:
Design Goal Design an Analog-to-Digital Conversion chip to meet demands of high quality voice applications such as: Digital Telephony, Digital Hearing.
Bandpass Sigma-Delta Modulator Michael Vincent Brian McKinney ECEN5007.
Large Area, High Speed Photo-detectors Readout Jean-Francois Genat + On behalf and with the help of Herve Grabas +, Samuel Meehan +, Eric Oberla +, Fukun.
The World Leader in High Performance Signal Processing Solutions Audio ADC/DACs Primer David Hossack.
Ph. Farthouat CERN ELEC 2002 ADC 1 Analog to Digital Conversion  Introduction  Main characteristics –Resolution –Dynamic range –Bandwidth –Conversion.
Digital to Analog Converters
Sigma Delta A/D Converter SamplerModulator Decimation Filter x(t) x[n]y[n] Analog Digital fsfs fsfs 2 f o 16 bits e[n] Over Sampling Ratio = 2f o is Nyquist.
Department of Electrical & Computer Engineering 1 ES585a - Computer Based Power System Protection Course by Dr.T.S.Sidhu - Fall 2005 Class discussion presentation.
A 10 bit,100 MHz CMOS Analog- to-Digital Converter.
Data Converters ELEC 330 Digital Systems Engineering Dr. Ron Hayne
DARPA Digital Audio Receiver, Processor and Amplifier Group Z James Cotton Bobak Nazer Ryan Verret.
ECE 4371, Fall, 2014 Introduction to Telecommunication Engineering/Telecommunication Laboratory Zhu Han Department of Electrical and Computer Engineering.
ACOE2551 Microprocessors Data Converters Analog to Digital Converters (ADC) –Convert an analog quantity (voltage, current) into a digital code Digital.
A 30-GS/sec Track and Hold Amplifier in 0.13-µm CMOS Technology
Filters and Delta Sigma Converters
INTERFACE WITH ANALOG WORLD
Analog to Digital conversion. Introduction  The process of converting an analog signal into an equivalent digital signal is known as Analog to Digital.
October 31st, 2005CSICS Presentation1 A 1-Tap 40-Gbps Decision Feedback Equalizer in a  m SiGe BiCMOS Technology Adesh Garg, Anthony Chan Carusone.
Seminar ON SMART SENSOR Submitted by : SUBIR KUMAR GHOSH Roll No. IN-14/04 Electrical & Instrumentation Deptt. B.E 7th Semester JORHAT ENGINEERING COLLEGE,
Digital Signal Processing and Generation for a DC Current Transformer for Particle Accelerators Silvia Zorzetti.
AD/DA Conversion Techniques - An Overview J. G. Pett  Introductory tutorial lecture for :- ‘Analogue and digital techniques in closed-loop regulation.
A 1V 14b Self-Timed Zero- Crossing-Based Incremental ΔΣ ADC[1] Class Presentation for Custom Implementation of DSP By Parinaz Naseri Spring
FE8113 ”High Speed Data Converters”. Course outline Focus on ADCs. Three main topics:  1: Architectures ”CMOS Integrated Analog-to-Digital and Digital-to-
A low-noise low-voltage continuous-time  modulator with digital compensation of excess loop delay Dr.S.Mehdi Fakhraie By: Mehrdad Ghobady.
Electronics Principles & Applications Fifth Edition Chapter 13 Integrated Circuits ©1999 Glencoe/McGraw-Hill Charles A. Schuler.
12/14/2010Sophia University Solid –State Circuits & Devices Laboratory 1 A low-power delta-sigma modulator using dynamic-source-follower integrators Ryoto.
ECE 4371, 2009 Class 9 Zhu Han Department of Electrical and Computer Engineering Class 9 Sep. 22 nd, 2009.
Analog to Digital Converters
ECE4006 Senior Design Project Linda Milor and Jay Schlag
THERMAL NOISE ESTIMATION IN SWITCHED-CAPACITOR CIRCUITS
Low Power, High-Throughput AD Converters
Figure Analog-to-digital conversion.. Figure The DAC output is a staircase approximation to the original signal. Filtering removes the sharp.
ECE 2799 Electrical and Computer Engineering Design ANALOG to DIGITAL CONVERSION Prof. Bitar Last Update:
Low Power, High-Throughput AD Converters
M. TWEPP071 MAPS read-out electronics for Vertex Detectors (ILC) A low power and low signal 4 bit 50 MS/s double sampling pipelined ADC M.
ASIC Development for Vertex Detector ’07 6/14 Y. Takubo (Tohoku university)
EKT 314/4 WEEK 5 : CHAPTER 3 SIGNAL CONDITIONING ELECTRONIC INSTRUMENTATION.
M. Atef, Hong Chen, and H. Zimmermann Vienna University of Technology
Design of the 64-channel ASIC: update DEI - Politecnico di Bari and INFN - Sezione di Bari Meeting INSIDE, December 18, 2014, Roma Outline  Proposed solution.
Low Power, High-Throughput AD Converters
High Gain Transimpedance Amplifier with Current Mirror Load By: Mohamed Atef Electrical Engineering Department Assiut University Assiut, Egypt.
B.Sc. Thesis by Çağrı Gürleyük
CTA-LST meeting February 2015
A Readout Electronics System for GEM Detectors
S-D analog to digital conversion
Σ-D Analog to Digital Converter for CMOS Image Sensors Nonu Singh (RIT, MicroE Co-Op) Background After fabricating an imaging sensor it needs to be characterized.
A Low Power Readout ASIC for Time Projection Chambers in 65nm CMOS
A Software Defined Radio for the Masses, Part 4
Department of Electrical Engineering and Automation
Analog-to-digital converter
Presentation transcript:

1HSSPG Georgia Tech High Speed Image Acquisition System for Focal-Plane-Arrays Doctoral Dissertation Presentation by Youngjoong Joo School of Electrical and Computer Engineering Georgia Institute of Technology February 12, 1999

2HSSPG Georgia Tech Outlines u Introduction u Background u Readout system architectures u Compact ovrsampling conversion u Photodetectors u Test u Conclusion and future work

3HSSPG Georgia Tech Introduction u Motivation Conventional focal-plane-arrays (FPAs) readout methods are not suitable for some scientific and engineering applications. 3Low readout speed 1MHz 1000X bit images 62THz 3Not scalable depending on the readout architecture 3Noise sensitive

4HSSPG Georgia Tech Introduction u Objective Design a new high speed scalable image acquisition system for FPAs. 3High frame rates (> 100kfps) 3Scalable 3Low noise

5HSSPG Georgia Tech Background A/D Converters A/D Converters Readout Systems Readout Systems Photo detectors DSP u Block diagram

6HSSPG Georgia Tech Photo detectors u Hybrid integration 3High responsivity 3High fill factor 3Substrate must be transparent 3Higher fabrication cost u Generate electronic signals and are located at the front end of the image acquisition system.

7HSSPG Georgia Tech Photo detectors u Monomaterial integration 3Compatibility with integration on-chip electronics 3Low cost 3Low absorption coefficient

8HSSPG Georgia Tech A/D converters u What is important for the focal-plane-applications? Size, robustness, variable resolution u Conventional A/D converters Flash ADC, Successive Approximation ADC Single slope ADC, Cyclic ADC, Oversampling ADC

9HSSPG Georgia Tech A/D converters *) modulator only

10HSSPG Georgia Tech Readout systems u Support an optimum interface between the detectors and the following signal processing stage.

11HSSPG Georgia Tech Readout systems u Serial readout system 3Noise reduction 3Not scalable 3Slow readout speed u Semi-parallel readout system 3Increase the readout speed 3Less sensitive to noise at the analog signal path

12HSSPG Georgia Tech Readout system architecture u Fully parallel readout system was designed as a scalable FPA readout system

13HSSPG Georgia Tech Readout system architecture u Signal path from image detector to signal processor Emitter driver Emitter Detector ReceiverComparatorSIMPil processor

14HSSPG Georgia Tech Readout system architecture u Two layer FPA system photomicrograph

15HSSPG Georgia Tech Readout system architecture u Readout speed comparison with same ADCs 64

16HSSPG Georgia Tech Readout system architecture u Readout speed comparison with different ADCs 288 X MHz15bits 4GHz

17HSSPG Georgia Tech Compact oversampling conversion u Oversampling ADC Oversampling converters trade speed for accuracy Analog input Noise shaping modulator PCM Oversampling clock f S Decimator and Digital LPF Nyquist clock f N 1-bit stream

18HSSPG Georgia Tech Compact oversampling conversion u Quantization noise of oversampling modulator Each doubling of the sampling frequency decreases the in- band noise by 3 dB. f0f0 f S /2 PSD Freq. Signal Quantization noise f0f0 f S /2 PSD Freq. Signal In band quantization noise Removed by low pass filtering

19HSSPG Georgia Tech Compact oversampling conversion u Modulation noise of higher order oversampling modulator Each doubling of the sampling frequency decreases the in- band noise by (3+6n) dB. f0f0 f S /2 PSD Freq. 1 st order quantization noise 2 nd order quantization noise Modulation noise

20HSSPG Georgia Tech Compact oversampling conversion u Current input oversampling modulator 3Oversampling loop linearity is improved. 3Amplifiers are removed from the feedback. 3Linear D/A conversion is available.

21HSSPG Georgia Tech Compact oversampling conversion u Current buffer 3Low input impedance 3Stabilize the detector bias voltage

22HSSPG Georgia Tech Compact oversampling conversion u Current D/A converter u Integrator Metal 3 Metal 2 Metal 1 Current in GND Current in Integrator

23HSSPG Georgia Tech Compact oversampling conversion u Comparator (G. M. Yin) Sampling rate : 100MHz, Input signal : 0.1V 10MHz Input signal Output signal

24HSSPG Georgia Tech Compact oversampling conversion u Overall system Current buffer & Photo detector Integrator & Current DAC Integrator Comparator

25HSSPG Georgia Tech Compact oversampling conversion u Overall system simulation results Integrator output voltage Modulator output Freq. PDF [dB] 50 kHz input signal Modulation noise

26HSSPG Georgia Tech Compact oversampling conversion u Circuit noise attenuation Delay xixi e di e ci yiyi wiwi where, e di = detector, current buffer, and current D/A converter noise and e ci = quantization and comparator noise.

27HSSPG Georgia Tech Compact oversampling conversion u Layouts 3To make a large detector, all the effort were applied to design a compact circuit. 3Input parts of the circuits were carefully designed not to overlapped with digital lines. 3To reduce the offset and improve the switching time of the comparator, all the components were carefully layout to make a matched comparator. 3When the capacitor was laid-out, metal 1 and metal 3 layers were connected to the GND to prevent the metal-substrate capacitor. 3The latch transistor size was optimized to drive a high capacitor load which is connected to several pixels through a long data line.

28HSSPG Georgia Tech Compact oversampling conversion u Photomicrographs Detector Circuits Capacitor Pad Circuits

29HSSPG Georgia Tech Photodetectors u Hybrid detectors 8X8 detectorstop contact

30HSSPG Georgia Tech Photodetectors u Monomaterial detectors V bias GND n+n+ n+n+ p+ p n+ p+

31HSSPG Georgia Tech Photodetectors u Monomaterial detectors 8X8 detectorstest structuresemitter driver

32HSSPG Georgia Tech Test u Test setup 3Arbitrary waveform generator (AWG2041) 3DC current sources (Keithley SMU 236) 3Sampling oscilloscope (Tektronix 11403A) 3Transient capture oscilloscope (Tektronix 3Multi-function optical meter (Newport 1835-c) 3Digital data acquisition card (CYDIO 192T) 350MHz 486 processor 3233MHz Pentium processor 3Newport coated ND filters

33HSSPG Georgia Tech Test u Electrical testing –Verify the functionality of the circuit 1.000uA 2.013V Oscilloscope DC current source

34HSSPG Georgia Tech Test u Electrical testing results Input = 0.03  AInput = 0.06  A

35HSSPG Georgia Tech Test u Slow speed testing setup

36HSSPG Georgia Tech Test u Slow speed testing : sampling rate=1MHz

37HSSPG Georgia Tech Test u Uniformity Low light intensityHigh light intensity

38HSSPG Georgia Tech Test u Linearity 64 pixels data6 bits linearity Saturation 6 bit range

39HSSPG Georgia Tech Test u Nonlinearity 3The nonlinearity of the small light intensity was not coming from the FPA system but the optical filter. 3The nonlinearity of the high light intensity was coming from the saturation of the system Measured data Test data

40HSSPG Georgia Tech Test u System noise The system noise is over than 8 bits.

41HSSPG Georgia Tech u High speed testing To obtain a 8 bit 100kfps image : 3oversampling ratio : 26 3modulator bandwidth : 2.6 MHz 3System bandwidth : 167 MHz Test

42HSSPG Georgia Tech u Modulator Test 2 MHz4 MHz

43HSSPG Georgia Tech u Output with 2.5MHz system frequency. Test Microscope lightRoom light

44HSSPG Georgia Tech u Output with 40MHz system frequency. Test Microscope lightRoom light

45HSSPG Georgia Tech u Output with 100MHz system frequency. Test Microscope lightRoom light

46HSSPG Georgia Tech u A new high speed readout system for FPAs were designed and tested. 3A new readout architecture was designed. 3A new current input first-order sigma-delta A/D modulator was designed. 3Two kinds of photo detectors were utilized. 3Several tests had been done to verify the proposed system. Conclusion and future works

47HSSPG Georgia Tech u To complete the fully parallel readout system for FPAs, two things need to be tested and verified. 3Test the speed of the through-wafer optical communication. 3Test with a microprocessor. 3The focal-plane-array chip and the microprocessor chip need to be stacked and test together. Conclusion and future works

48HSSPG Georgia Tech Whole system