Chapter 8: Memory-Management Strategies 1

Administration n Midterm exams are returned to you l TA will talk about solution and grading guide l Likely to scale up everyone’s grades n Nachos #4 will be on the course webpage l Due in 3 weeks 2

Plable (Yumiko Tanaka) 3

Outline n Memory address n Swapping n Memory-management techniques & hardware l Contiguous memory allocation l Non-contiguous memory allocation  Paging  Segmentation n Example: The Intel Pentium 4

Background n Program must be brought (from disk) into memory and placed within a process for it to be run n Main memory and registers are only storage CPU can access directly l Register access in one CPU clock (or less) l Main memory can take many cycles (5-10 ns) l Cache sits between main memory and CPU registers n Memory management techniques (multiprogramming) must do l Memory access protection (process/kernel, process/process) l Fast memory access 5

Basic Hardware n A pair of base & limit registers define the logical address space n Hardware address protection with base & limit registers 6

Address Binding n Recall that a process must be loaded into memory (address space) from disk before execution l Instruction & data must be given memory address l int count; void sort() n Address binding is about when/how to give the program (variables & functions) memory addresses l Compile time – how? l Load time – how? l Execution time – how? 7

Address Binding n Compile time: If memory location known a priori, absolute code can be generated; must recompile code if starting location changes n Load time: If memory location known at load time, generate relocatable code at compile time n Execution time: Binding delayed until run time if the process can be moved during its execution from one memory segment to another. l Most modern general purpose OSes, why? l Need hardware support for address maps (e.g., base and limit registers) 8

Multistep Processing of a User Program

Logical vs. Physical Address Space n An common concept used in memory management techniques: l Logical address space is bound to a separate physical address space during process execution time n Logical address – generated by the CPU, also called virtual address l Compile-time and load-time n Physical address – address used by the physical memory unit l Translated from logical address during execution time using the MMU hardware (memory-management unit) l Start with a simple one …. 10

Dynamic relocation using a relocation register

Memory-Management Unit ( MMU ) n Hardware device that maps virtual to physical address n In MMU scheme, the value in the relocation register is added to every address generated by a user process at the time it is sent to memory n The user program deals with logical addresses; it never sees the real physical addresses 12

Dynamic Loading n Often not all the program code is executed by CPU, e.g., error handling code. l Waste time loading all program code … l Also delay program startup time l How to solve them? n Dynamic loading l Routine is not loaded until it is called l Better memory-space utilization; unused routine is never loaded 13

Dynamic Linking n Often a program uses share libraries, e.g., c library. l How do you “load” them? l Extend the dynamic loading concept n Dynamic linking l Linking postponed until execution time l Small piece of code, stub, used to locate the appropriate memory-resident library routine l Stub replaces itself with the address of the routine, and executes the routine l Also work for library update (version) l System also known as shared libraries 14

Swapping n Often, a system runs out of memory with more processes than it can accommodate. l It need to get rid of one (or more) lower-priority process to free up spaces l How do you solve this issue? 15

Swapping n A process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued execution n Backing store – fast disk large enough to accommodate copies of all memory images for all users; must provide direct access to these memory images n Roll out, roll in – swapping variant used for priority-based scheduling algorithms; lower-priority process is swapped out so higher-priority process can be loaded and executed n Major part of swap time is transfer time; total transfer time is directly proportional to the amount of memory swapped n Modified versions of swapping are found on many systems (i.e., UNIX, Linux, and Windows) n System maintains a ready queue of ready-to-run processes which have memory images on disk 16

Swapping 17

Memory management techniques n Contiguous memory allocation n Non-contiguous memory allocation l Paging l Segmentation 18

Contiguous memory allocation n Main memory usually into two partitions: l Resident operating system, usually held in low memory with interrupt vector l User processes then held in high memory n Relocation registers used to protect user processes from each other, and from changing operating-system code and data l Base register contains value of smallest physical address l Limit register contains range of logical addresses – each logical address must be less than the limit register l MMU maps logical address dynamically 19

Contiguous memory allocation 20

Simple but with problem(s) n Hole – block of available memory; holes of various size are scattered throughout memory n When a process arrives, it is allocated memory from a hole large enough to accommodate it n Operating system maintains information about: a) allocated partitions b) free partitions (holes) n What problems can hole(s) create? OS process 5 process 8 process 2 OS process 5 process 2 OS process 5 process 2 OS process 9 process 2 process 9 21

Dynamic Storage-Allocation Problem n How to satisfy a request of size n from a list of free holes? n First-fit: Allocate the first hole that is big enough n Best-fit: Allocate the smallest hole that is big enough; must search entire list, unless ordered by size l Produces the smallest leftover hole n Worst-fit: Allocate the largest hole; must also search entire list l Produces the largest leftover hole n First-fit and best-fit better than worst-fit in terms of speed and storage utilization 22

Fragmentation in contiguous memory allocation n External Fragmentation – total memory space exists to satisfy a request, but it is not contiguous n Internal Fragmentation – allocated memory may be slightly larger than requested memory; this size difference is memory internal to a partition, but not being used n Reduce external fragmentation by compaction l Shuffle memory contents to place all free memory together in one large block l Compaction is possible only if relocation is dynamic, and is done at execution time l Costly & I/O problem  Latch job in memory while it is involved in I/O  Do I/O only into OS buffers 23

How to get rid of external fragmentation? n What is the most widely used technique in computer science? n How about not “Contiguous” memory allocation? 24

Paging n Logical address space of a process is noncontiguous n Divide physical memory into fixed-sized blocks called frames l Size is power of 2, typically 4K or 8K. n Divide logical memory into blocks of same size called pages n Keep track of all free frames n To run a program of size n pages, need to find n free frames and load program n Set up a page table to translate logical to physical addresses n Internal fragmentation 25

Address Translation Scheme n Address generated by CPU is divided into: l Page number (p) – used as an index into a page table which contains base address of each page in physical memory l Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit l For given logical address space 2 m and page size 2 n page number page offset p d m - n n 26

Paging Hardware 27

Paging Model of Logical and Physical Memory 28

Paging Example 32-byte memory and 4-byte pages

Free Frames Before allocation After allocation 30

A Slow Implementation of Page Table n Page table is kept in main memory n Page-table base register (PTBR) points to the page table n Page-table length register (PRLR) indicates size of the page table n What is the memory access performance? l Two memory accesses. One for the page table and one for the data/instruction. n How to make it faster (with help from hardware)? 31

Translation Look-Aside Buffer n The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs) n Associative memory – parallel search on very fast cache n Address translation (p, d) l If p is in associative register, get frame # out l Otherwise get frame # from page table in memory Page #Frame # 32

Translation Look-Aside Buffer n Some TLBs store address-space identifiers (ASIDs) in each TLB entry – uniquely identifies each process to provide address-space protection for that process 33

Paging Hardware With TLB 34

Effective Access Time n Associative Lookup = 20 ns time unit n Assume memory cycle time is 100 ns n Hit ratio – percentage of times that a page number is found in the associative registers; ratio related to number of associative registers n Hit ratio  = 90% n Effective Access Time (EAT) EAT = ( ) 90% + ( )(1 – 90%) = =

Memory Protection n Memory protection implemented by associating protection bit with each frame n Valid-invalid bit attached to each entry in the page table: l “valid” indicates that the associated page is in the process’ logical address space, and is thus a legal page l “invalid” indicates that the page is not in the process’ logical address space 36

Valid (v) or Invalid (i) Bit In A Page Table 37

Shared Pages n Shared code l One copy of read-only (reentrant) code shared among processes (i.e., text editors, compilers, window systems). l Shared code must appear in same location in the logical address space of all processes n Private code and data l Each process keeps a separate copy of the code and data l The pages for the private code and data can appear anywhere in the logical address space 38

Shared Pages Example 39

Structure of the Page Table n Often a page table can become large l 32-bit address space with 4 KB (2 12 ) page l 2 20 paging entries (1M), each entry 4B = 4MB l How about 64-bit address space? l It may not be allocated contiguously in physical memory l It may not fit into physical memory n How to solve these issues? l Hierarchical Paging l Hashed Page Tables l Inverted Page Tables 40

Hierarchical Page Tables n Page the page table l Two or multi-level page table 41

Two-Level Paging Example n A logical address (on 32-bit machine with 1K page size) is divided into: l a page number consisting of 22 bits l a page offset consisting of 10 bits n Since the page table is paged, the page number is further divided into: l a 12-bit page number l a 10-bit page offset n Thus, a logical address is as follows: n where p i is an index into the outer page table, and p 2 is the displacement within the page of the outer page table page number page offset pipi p2p2 d

Address-Translation Scheme 43

Three-level Paging Scheme n 64-bit address n What about the cost of memory access as # of levels increases (in a TLB miss)? n Any solutions? (alternative to the tree data structure) 44

Hashed Page Tables n Common in address spaces > 32 bits l Hierarchical paging is too slow (in case of a TLB miss) n The virtual page number is hashed into a page table. This page table contains a chain of elements hashing to the same location. n Know what is a hash table? n Virtual page numbers are compared in this chain searching for a match. If a match is found, the corresponding physical frame is extracted. 45

Brief Introduction on Hash table n Why hash table? n Suppose that we want to store 10,000 students records (each with a 5-digit ID) in a given container. l A linked list implementation would take O(n) time. l A height balanced tree would give O(log n) access time. l Using an array of size 100,000 would give O(1) access time but will lead to a lot of space wastage. n Is there some way that we could get O(1) access without wasting a lot of space? l Consider the case of large 64-bit address space with sparse entries (limited by physical memory & hard disk) 46

Example 1: Illustrating Hashing n Use the function f(r) = r.id % 13 to load the following records into an array of size Al-Otaibi, Ziyad Al-Turki, Musab Ahmad Bakeer Al-Saegh, Radha Mahdi Al-Shahrani, Adel Saad Al-Awami, Louai Adnan Muhammad Al-Amer, Yousuf Jauwad Al-Helal, Husain Ali AbdulMohsen

Example 1: Introduction to Hashing (cont'd) HusainYousufLouaiZiyadRadhaMusabAdel h(r) = id % 13IDName Al-Otaibi, Ziyad Al-Turki, Musab Ahmad Bakeer Al-Saegh, Radha Mahdi Al-Shahrani, Adel Saad Al-Awami, Louai Adnan Muhammad Al-Amer, Yousuf Jauwad Al-Helal, Husain Ali AbdulMohsen

Hash Tables n Hash function H: search key -> [0.. N-1] l Example: H(x) = x mod N l x (search key) = 64-bit address l N = size of the hash table l H(x) = hash table index n Hash tables are sometimes referred to as scatter tables. n Typical hash table operations are: l Search l Insertion l Deletion

Search (%13 = 10) HusainYousufLouaiZiyadRadhaMusabAdel h(r) = id % 13IDName Al-Otaibi, Ziyad Al-Turki, Musab Ahmad Bakeer Al-Saegh, Radha Mahdi Al-Shahrani, Adel Saad Al-Awami, Louai Adnan Muhammad Al-Amer, Yousuf Jauwad Al-Helal, Husain Ali AbdulMohsen

Insert Husain ( % 12 = 1) HusainYousufLouaiZiyadRadhaMusabAdel h(r) = id % 13IDName Al-Otaibi, Ziyad Al-Turki, Musab Ahmad Bakeer Al-Saegh, Radha Mahdi Al-Shahrani, Adel Saad Al-Awami, Louai Adnan Muhammad Al-Amer, Yousuf Jauwad

Delete Ziyad ( % 13 = 6) HusainYousufLouaiZiyadRadhaMusabAdel h(r) = id % 13IDName Al-Otaibi, Ziyad Al-Turki, Musab Ahmad Bakeer Al-Saegh, Radha Mahdi Al-Shahrani, Adel Saad Al-Awami, Louai Adnan Muhammad Al-Amer, Yousuf Jauwad Al-Helal, Husain Ali AbdulMohsen

Types of Hashing n There are two types of hashing : 1. Static hashing: In static hashing, the hash function maps search-key values to a fixed set of locations. – In case of collision -> add overflow entries 2. Dynamic hashing: In dynamic hashing a hash table can grow to handle more items. The associated hash function must change as the table grows. – In case of collision -> grow the hash table

Hashed Page Table

Inverted Page Table n To keep the page table small l One entry for each frame of the physical memory n Each entry has (pid, page-number) n Given (pid, page-number), how to find the physical frame? l Very slow: scan entries in the table l Fast: build a hash table with the hash key = (pid, page-number) 55

Inverted Page Table Architecture

Segmentation n Memory-management scheme that supports user view of memory n A program is a collection of segments. A segment is a logical unit such as: l main program, l procedure, l function, l method, l object, l local variables, global variables, l common block, l stack, l symbol table, arrays 57

User’s View of a Program

Logical View of Segmentation user spacephysical memory space

Segmentation Architecture n Logical address consists of a two tuple:, n Segment table – maps two-dimensional physical addresses; each table entry has: l base – contains the starting physical address where the segments reside in memory l limit – specifies the length of the segment n Segment-table base register (STBR) points to the segment table’s location in memory n Segment-table length register (STLR) indicates number of segments used by a program; segment number s is legal if s < STLR 60

Segmentation Architecture (Cont.) n Protection l With each entry in segment table associate:  validation bit = 0  illegal segment  read/write/execute privileges n Protection bits associated with segments; code sharing occurs at segment level n Since segments vary in length, memory allocation is a dynamic storage-allocation problem n A segmentation example is shown in the following diagram 61

Segmentation Hardware

Example of Segmentation

Example: The Intel Pentium n Supports both segmentation and segmentation with paging n CPU generates logical address l Given to segmentation unit  Which produces linear addresses l Linear address given to paging unit  Which generates physical address in main memory  Paging units form equivalent of MMU 64

Logical to Physical Address Translation in Pentium

Intel Pentium Segmentation

Pentium Paging Architecture

Linear Address in Linux Broken into four parts:

Three-level Paging in Linux

End of Chapter 8 70