Computer Architecture Lecture 5: Addressing modes Piotr Bilski

Why do we need different addressing modes? Real or virtual memory space is larger than space referred to by the argument (too small number of bits) A compromise between the address range and simplicity of the address fetching is needed

Real (effective) and virtual address The real address is the address of the physical location in the memory Virtual address (effective address - EA) is the address treated as the instruction argument Translation of the virtual address into the real one depends on the organization of the memory

Symbols used EA – effective address R – content of the address field in the instruction referring to the registers A – content of the addresss field in the instruction (X) – content of the location X

Addressing modes Immediate Direct Indirect Register Register indirect Displacement (indexed) Stack

Immediate mode Operation code Argument value The argument is stored in the instruction using Two’s complements format. Therefore, this number can not be too large.

Direct mode Operation code Argument address Argument memory EA = A

Indirect mode Operation code Address storing information about the address of the argument Argument memory EA = (A) Nesting possible!

Register mode Operation code Name (register number) Argument registers EA = R

Register indirect mode Operation code Address registers Name (register number) memory Argument EA = (R)

Displacement mode Operation code Argument address Address registers Name (register number) memory Argument EA = (A)

Displacement mode (cont.) Relative addressing (R=PC) Addressing with the base register (efficient for the segmented memory) – EA=R+A Indexing (different interpretation of the register and address field that when using base register) – EA=A+R

Displacement addressing (cont.) Addressing with the base register Indexing (uses dedicated indexing register) Operation code Displacement value Register with argument address Operation code Argument address Register with displacement

Stack mode Operation code Argument address Stack register registers stack

Address types Physical – location of the address in the memory Logical – location of the address in relation to the program entry point Base – entry point address

Memory organization from the operating system level Paged memory (model invisible for the programmer) – memory is divided into small fragments (page frames), assigned to the fragments of the programs Segmented memory (model available for the programmer) – assures separate addressing space for every process

Partitioning with the predefined size Division of the memory into fragments of the predefined sizes (constant or varying) 16 MB (OS) 16 MB 16 MB (OS) 4 MB 8 MB 16 MB

Partitioning with the dynamic size Division of the memory into fragments of the sizes depending on the processes requirements 16 MB (OS) 48 MB free 16 MB (OS) Process 1 (20 MB) 28 MB free 16 MB (OS) Process 1 (20 MB) Process 2 (16) MB 12 MB free 16 MB (OS) Process 3 (18 MB) Process 2 (16) MB 12 MB free

Paging memory Process A: Page 0 Page 1 Page 2 Free frames: memory Page 0 Page 1 Page 2 Page table of the process A:

Physical and logical addresses in the paging structure Logical address 1 30 Page table of the process A: memory Page 0 Page 1 Page 2 Physical address 12 30

Translation Lookaside Buffer Cache memory for the recent memory addresses translations Very fast, but small size TLB cooperates with the „real” cache memory Bad design can lead to the system’s malfunctions (see Phenom processors)!

Translation Lookaside Buffer (TLB) START STOP Checking TLB Entry in TLB? YES NO Access to the page table Page in memory? Physical address generation Actualize TLB Page fault handling NO YES

Segmentation Easy management of the data structures of varying size Ability to grant individual rights of the processes to the subsequent segments Ability to use the segment by multiple processes Addressing: segment number + relative address

Pentium address spaces Non-segmented, non-paged memory (virtual address = physical address - drivers) Non-segmented, paged memory (BSD) Segmented, non-paged memory Segmented, paged memory (UNIX System V)

Pentium II Segmentation 2 bits of the segment pointer are used for the protection mechanism Relative address allows addressing 2 32 = 4 GB of memory The overall amount of addressable memory is 2 16 x 2 32 = 64 TB Access of the process to the segment depends on the accessibility level (indicated by the number from 0 – the highest to 3 – the lowest) Virtual address Segment pointer 16 bits Relative address 32 bits

Segment Selector and Descriptor Index PRVTI Base 15-0 Segment border 15-0 Base GS G AVLAVL D/BD/B Base P DPL S Type

Pentium II Paging The page directory contains 1024 entries, which divide the memory into 1024 pages groups Each pages group contains up to 1024 entries Every page has size of 4 kB or 4MB (depending on the PSE bit) Page tables can be contained in the virtual memory Translation Lookaside Buffer contains up to 32 entries of the page tables for the particular page directory

Paging/Segmentation in Pentium II

Pentium addressing modes Pentium has six segment registers (SR) to hold addresses of the first segments Segment descriptor register is related to the segment register (contains segment access rights and its length) Additional registers (base and index) help to assemble address

Pentium addressing modes (cont.) Immediate (Arg = A) Register (AL = R) Displacement (AL = (SR) + A) Base register (AL = (SR) + (B)) Base register with displacement (AL = (SR) + (B) + A) Scaled index with displacement (AL = (SR) + (I) x S + A) Base register with index and displacement (AL = (SR) + (B) + (I) + A) Base register with scaled index and displacement (AL = (SR) + (I) x S + (B) + A) Relative (AL = (PC) + A)

Illustration of the Pentium addressing modes Segment register Descriptor register Selector Linear address Base register Indexing register Scale Displacement Memory Segment base address Border

PowerPC memory management RISC architecture – simple addressing modes! Implementation depends on the architecture (32 or 64 bit) Block address translation mechanism is used as the alternative to the paging mechanism

Effective and real address of PowerPC Effective address Real address Segment PageByte selector Real page numberByte alignment

PowerPC addressing modes Load/store architecture (also with update) –Indirect (AE = (BR) + D ) –Indexed indirect (AE = (BR) +(IR)) Branch address –Absolute (AE = I) –Relative (AE = (PC) +I) –Indirect (AE = (L/CR)) Arithmetic –Register fixed position (AE = GPR) –Immediate (Arg = I) –Register floating position (AE = FPR)

Instruction format Instruction length is limited by the breadth of the applied buses Instruction length should be equal to the breadth of the bus or its multiplicity A compromise between the bit number required for the instruction code and address space Instructions containing codes of varying length are more flexible

Instruction Design Criteria Number of addressing modes Number of operands Number of registers and their sets Address range Address granularity level (byte or word addressing?)

Format example: PDP-8 Instructions and data 12 bit long One register – accumulator Memory is divided into the pages 2 7 = 128 words long The eight bit is a pointer to the page number

PDP-8 instructions Operation D/I Z/CDisplacement DeviceOperation code x CLA CLL CMA CML RAR RAL BSW IAC Memory related instructions Input/output instructions Microoperations and register related instructions

PDP-10 instructions Instruction elements are orthogonal Only direct addressing 36-bit instruction and data Operation Register I Index registerMemory address

Pentium instruction format Prefixes Oper. code ModR/M SIB Displacement Immediate 0-4 B 1-2 B 0-1 B 0-1 B 0-4 B 0-4 B Address specifier

PowerPC instruction format All instructions are 32-bit long! 6 b 5 b 5 b 16 b Operation Options/desti- Options/source nation register register