Presenter : Cheng-Ta Wu Pieter van der Wolf and Jeroen Geuzebroek Synopsys Eindhoven, The Netherlands Design, Automation & Test in Europe Conference & Exhibition (DATE),

Advanced SoCs integrate a diverse set of system functions that pose different requirements on the SoC infrastructure. Predictable integration of such SoCs, with guaranteed Quality-of-Service (QoS) for the real-time functions, is becoming increasingly challenging. We present a structured approach to predictable integration based on a combination of architectural principles and associated analysis techniques. We identify four QoS classes and define the type of QoS guarantees to be supported for the two classes targeted at real-time functions. We then discuss how a SoC infrastructure can be built that provides such QoS guarantees on its interfaces and how network calculus can be applied for analyzing worst-case performance and sizing of buffers. Benefits of our approach are predictable performance and improved time- to-market, while avoiding costly over-design. 2

Predictable integration of such diverse set of system functions, with guaranteed Quality-of-Service (QoS) for the real-time functions, is particularly challenging when cost efficiency demands sharing of resources like interconnect and memory.  Identify four QoS classes  Built SoC infrastructure (memory control, interconnect) to support the defined QoS 3

4 [7] SoC architecture template [8] SoC infrastructure elements [9] Memory controller This Paper survey Interconnect Enable data flow analysis for real- time stream processing function

Latency critical  The client latency will direct impact the system performance Latency tolerant  The client uses input/output buffer to load /store data to memory. No real-time guarantee  No hard deadline such as CPU Real-time guarantee  Has hard deadline such as video processing(frame/s) 5

Average Latency(AL)  It’s a frame-based audio processing on a CPU and is the key to efficient and correct integration of such audio processing function. Latency Rate(LR)  This implies that a throughput (p) is guaranteed after an initial latency  It is a video function that streams data to / from memory. 6

Such specification is used as input for determining the type of infrastructure, the size of buffers, and the choice of arbiters and arbiter settings. 7

Multi-ported memory controller allows QoS requirements to be explicitly programmed per port. In typical situations the LL ports are served with the highest priority The memory controller explicitly accounts the service provided on its AL / LR ports. When an account indicates that a port is in danger of being underserved, this port takes priority over the LL ports in order to ensure that its guarantee is met. 8

The memory controller implements the accounting-based arbitration. It supports the LL, BE, and RT Streaming QoS classes. Priorities can be assigned to ports of the LL/BE classes to control the arbitration among them. The simulations have been run on the actual RTL of a 32-bit memory controller that takes into account all (timing) penalties of the attached DRAM devices, in this case two 1Gbit DDR2-800 x16 devices. LL port ->CPU with low latency requirements P1,P2 port->video with real time requirements BE port-> peripherals 9

First experiment (CPU HIGH): fixed priority, LL port has the highest priority. Second experiment (CPU LOW): fixed priority, P1/P2 have the highest priority. Last experiment (QoS): deploy the accounting-based arbitration, initially the LL port has the highest priority. 10