CMS Annual Review September 2004Geoff Hall1 Tracker Off-detector Electronics On-detector electronics production approaching completion procuring spares Off-detector electronics FED & FEC development complete substantial software development Power supplies prototyping of cavern version successful tender action complete ESRs completed final one: Off-detector electronics November 2003 Grounding and shielding Fine tuning of systems already demonstrated in lab and beam tests

CMS Annual Review September 2004Geoff Hall2 FEDv1 -first prototype 9U VME64x PCB 14 layers (incl 6 power & ground) ~ 6 K components (smallest 0402) ; ~ 25 K tracks BGAs largest mm pitch 96 ADC channels : AD9218 Dual package MHz Half Analogue circuitry on Secondary Side JTAG Boundary Scan  6 FEDv1 boards delivered to CERN for Large Scale Assembly centres (4 used in 25 nsec test beam June 2004)  5 FEDv1 boards kept in UK for Design Tests

CMS Annual Review September 2004Geoff Hall3 FEDv1 Manufacture History  Sep 2003  5 FEDv1 boards under test. (PCB and Assembly by separate small companies) All boards working well. Only manufacturing minor faults.  Oct 2003  Further 6 FEDv1 made. (same manufacturers) Major problems on all boards. Shorts under many BGAs. Rework of BGAs attempted. After initial success on 2 boards failed on next 4. Problem believed due to uncured solder resist ink leeching from vias of bare PCBs. Precise diagnosis difficult, plus change of metal finish (Ni/Gold -> Immersion Tin).  Nov Jan 2004 Identified candidate medium size companies suitable for 500 production boards. Providing combined PCB and Assembly with guarantees. Offer advanced Quality Controls, Auto Optical Inspection, X-ray (in house), BScan.  Mar 2004  Manufactured 6 FEDv1 with one identified company. Very professional production. No BGA problems. All boards working well.

CMS Annual Review September 2004Geoff Hall4 FEDv1 Design Testing Objectives Validate final designdone large scale assembly acceptance testsunder way Hardware few issues studied and resolved during testing 100 kHz L1 S-LINK 80 MHz. TTC and TCS Interfaces verified Analogue performance excellent. Optical inputs using FED Opto-Tester board. To optimise OptoRx (1% settling in 15ns) some FE component values need final tuning. Power/temp requirements finalised. Standard LHC crates satisfactory. Firmware complete and working for assembly test use Used in 25 nsec Test Beams June Few minor issues (as expected!) under investigation. Software fully integrated in CMS Tracker DAQ framework. Test bench Framework for essential Assembly Plant Testing nearly ready

CMS Annual Review September 2004Geoff Hall5 FEDv2 pre-Production Board Aim to be final production version - minimal changes from v1  Power Block : General improvements.  QDR Memory : Replacement part (pin compatible) identified.  FE FPGA : Use larger 2M gate (pin compatible) part.  ADC : AD9218 Device bug. Reduce gain by half. Simple mod.  FPGA Configuration : VME Boot device reprogram via JTAG cable.  S-LINK & TCS Signals : New 6U VME Transition Card.  FE Analogue : Tune few components for optimal matching to Optical Link Status First 2 boards received in August. Tests proceeding well. Boundary Scan passed. VME crate tests in progress  Plan to make a further ~20 before end of 2004 for Full Crate tests.

CMS Annual Review September 2004Geoff Hall6 Testing at Assembly Plant 1. Custom Tests at Assembly Plant BScan, VME crate 3. Tests at CERN Prevessin Readout Integration 2. Tests at RAL & IC OptoRx, Full crate 4. Installation at CMS USC55 0. Quality Controls during Assembly process AOI, X-ray Boundary Scan Testing for Digital Testing by Assembly plant operatives VME Crate Testing for Analogue Test Flow from Assembly Plant to USC boards to test over 10 months. Essential to catch any manufacturing faults early.

CMS Annual Review September 2004Geoff Hall7 FED Schedule (v 1.6 March 2004) Production Plans Q1/2004 : Complete tests of FEDv1 design. Done. Finalise design changes for FEDv2. Done. Sign off against FED User Requirements Document. Done. Q2/2004 : Implement changes for FEDv2 and review. Done. Q3/2004 : Manufacture couple of FEDv2s. Done. Q4/2004 : Test FEDv2. In progress. Manufacture further 20 FEDv2s. All parts in hand except QDR memories on order. Q2/2005 -> Q2/2006 : Manufacture 500 ~ 50 / month. Fully test batches in UK. Ship to CERN in batches of 50. Re-test at CERN/Prevessin prior to CMS installation. EU Tender Procedure for PCB/Assembly Q1/2004 : Place OJEC advert, invite Expressions of Interest. Done. Q3/2004 : Dispatch calls for Quotes. Identify 2-3 companies. In progress. Q4/2004 : Select company. Detailed negotiations re Testing, delivery schedules…etc Q1/2005 : Award contract. Expect to tune this schedule in response to availability of B904 and USC55

CMS Annual Review September 2004 Geoff Hall8 VME FEC  Support for 1~8 control rings per board.  VME 9U board.  VME64x compatible.  Control information passes through the VME bus.  Fast Timing Signals passes through the TTC link. VME interface FPGA mFEC TTCrx QPLL Local Bus Fast Timing signals JTAG ECAL TTC/TTS bus VME bus TTC link Trigger FPGA See also Kostas Kloukinas ECAL AR for all details Now use for TK + ECAL, pixels, Preshower

CMS Annual Review September 2004 Geoff Hall9 VME FEC 1 st Prototype VME backplane TTC/TTS bus mFECs TTC input VME Interface FPGA Trigger FPGA 6 Layer board Final version and already in use

CMS Annual Review September 2004 Geoff Hall10 FEC Production  Tracker: 352 control rings: 44 VME FEC boards + spares total with ECAL, etc 112 VME boards mFECs  First VME PCB prototype: work, but manufacturing issue excessive bending after thermal cycle (solder components)  VME FEC Pre-Production PCBs at CERN this week. adjusted stacking of the FR4 layers  mFEC Pre-Production Run (50 off) Available late September.  Final Production (PCB fabrication + assembly + testing) mFECsJan Jun FEC boardsJan Jun. 2005

CMS Annual Review September 2004Geoff Hall11 Power supplies Two prototypes produced Cavern and counting room variants Performance looks excellent B-field tests done Radiation tests done Lab tests show good performance noise isolation hardware protection and current limiting overvoltage protection efficiency 70-85% (load dependent) used in beam tests with long cables giving excellent results

CMS Annual Review September 2004Geoff Hall12 Modules Variants very similar - one allows cavern operation Sufficiently B-field and radiation tolerant Recent improvements in transformers optimise size

CMS Annual Review September 2004Geoff Hall13 Tender & Schedule Tender action complete Technical performance of two variants essentially identical Cavern Supply had required magnetic field and radiation tolerance Cost saved by PS in the Cavern was between MCHF.. Cavern solution adopted June 2004 INFN adjudication committee accept CAEN offer Production - if order placed before October 2004 Begin Q Ramp to ~65 /month Complete deliveries in Q1 2006

CMS Annual Review September 2004Geoff Hall14 Delivery Schedule Red = SST + pixels

CMS Annual Review September 2004Geoff Hall15 Commissioning Separate detector support activities from commissioning Stable DAQ and hardware needed for large scale assembly Prevessin 904 for pre-commissioning phase USC55/UXC for final phase NB TK DAQ essentially ready and working (XDAQ) Adapt plans to availability of space and plant Eg FEDs 1) Quality control in company during assembly 2) Tests at assembly plant (JTAG, Self Test) Crate and software provided by IC-RAL, tests all functionality except ORx’s 3) Final acceptance of boards at Imperial and RAL optical tests, and soak test 4) Test at CERN 904 with FEC, TTC, trigger etc should verify previous results prior to move to cavern 5) Installation in system at CERN

CMS Annual Review September 2004Geoff Hall16 Conclusions No showstoppers in sight Well advanced with hardware, pre-production, evaluation and integration, including software Production plans almost complete Main issues Quality of production (and associated cost & effort) Adapting commissioning plans to requirements

CMS Annual Review September 2004Geoff Hall17 Spare slides

18 FED Overview VME-FPGA TTCrx BE-FPGA Event Builder Buffers FPGA Configuration Compact Flash Power DC-DC DAQ Interface 12 Front-End Modules x 8 Double-sided board CERN Opto- Rx Analogue/Digital 96 Tracker Opto Fibres VME Interface Xilinx Virtex-II FPGA Modularity 9U VME64x Form Factor Modularity matches Opto Links 25,000 Si strips / FED 440 FEDs in Total. 8 x Front-End “modules” OptoRx/Digitisation/Cluster Finding Back-End module / Event Builder VME module / Configuration Power module Other Interfaces: TTC : Clk / L1 / BX DAQ : Fast Readout Link TCS : Busy & Throttle VME : Control & Monitoring JTAG : Test & Configuration FE-FPGA Cluster Finder TTC TCS Temp Monitor JTAG TCS : Trigger Control System 9U VME64x Input ~ 3 GBytes/sec after Zero Suppression : Output: ~ 200 MBytes/sec

CMS Annual Review September 2004Geoff Hall19 Firmware and FPGAs Delay x 24FE x 8 BE x 1 VME x 1 Delay FPGA: ADC Coarse and Fine Clock Skewing. FE FPGA: Scope and Frame Finding modes. BE FPGA: Event building, buffering and formatting. VME FPGA: Controls and Slow Readout path. Baseline of 4 FPGA Final Designs working Xilinx Virtex II FPGAs up to 2M equiv gates each

CMS Annual Review September 2004Geoff Hall20 S-LINK VME Transition Card Simple 6U board: Provides interface between FED and Slink Transmitter Provides access to FED Throttle signals DAQ Slink Transmitter Slink Transition Card Ethernet Connector FED Slink Data & Control Signals FED Throttle Signals VME Backplane 6U 3 Transition Cards in manufacture by end July. Now back for test in September. (compatible with both FEDv1 and FEDv2)